On many boards I've seen, there are little copper dots used for the purpose of "Copper Thieving". They're small round copper dots connected to nothing and arranged in an array. Supposedly they're for balancing the copper on the boards to improve manufacturability, but no explanation I've heard has convinced me that they're needed or useful. What are they for and do they actually work?

Below is an example with squares.

 Example with Squares

  • 3
    \$\begingroup\$ This is a real-world example. \$\endgroup\$
    – mng
    Commented Oct 16, 2013 at 23:51
  • \$\begingroup\$ I usually talk to the vendor making the PCB(s) and ask them to do a DFM (design for manufacture) review. The vendor best knows their capabilities and process limits and should be able to advise if features like this are necessary. Then it's up to you as a designer to add them - which keeps you in control of the design. Some PCB manufacturing companies will publish a design rules guide which may have this information in anyway. \$\endgroup\$
    – AndyK
    Commented Jun 15, 2015 at 10:32

6 Answers 6


Copper dots (or grid/solid fill) are used mainly to balance the thermal properties of the board, to minimize twist and warp as the board goes through the thermal cycling associated with reflow and improving yield.

A secondary purpose for them is to reduce the amount of copper that needs to be etched away from the board, balancing the etching rates across the board and helping to make the etching solution last longer.

If the PCB designer did not explicitly "pour" copper fill into the open areas of the board's outer layers, the fabrication house will often add the small disconnected dots, because these will have the least effect on the electrical properties of the board.

  • 9
    \$\begingroup\$ I would hope the fab wouldn't just fill empty space with a pattern without at least asking; what if it's empty for isolation purposes, or RF, etc? What fabs do this so I can stay away? \$\endgroup\$
    – Nick T
    Commented Oct 16, 2013 at 20:19
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    \$\begingroup\$ @NickT, Fabs that are geared to high(ish) volumes seem to always want to do this. They will ask first. Rather than wait for the Engineering Query, it's good to add a fab note indicating whether you will accept thieving or not. \$\endgroup\$
    – The Photon
    Commented Oct 16, 2013 at 20:30
  • 6
    \$\begingroup\$ Unfortunately this answer is incorrect - but a very common misunderstanding. \$\endgroup\$ Commented May 17, 2014 at 8:05
  • \$\begingroup\$ @BenVoigt This answer talks about twist&warp + etching. My answer talks about plating. Very different answers. Thanks for reading and helping improve the site. \$\endgroup\$ Commented Aug 30, 2018 at 16:20
  • \$\begingroup\$ @RolfOstergaard: Ah, it would be clearer if in your answer you specified whether you agree or disagree that thieving helps with etching. \$\endgroup\$
    – Ben Voigt
    Commented Aug 30, 2018 at 16:33

Unfortunately the other 3 answers to the question are incorrect, but helps keeping a common misunderstanding alive :-)

Thieving is added to the outer layers in order to help a more balanced chemical process for the plating.

Also notice that there is no need to "balance copper" (or stackups for that matter) in modern PCB fabrication to avoid "warped boards".

I wrote about this on my blog recently. You can find other references on the net.

  • \$\begingroup\$ Thanks all for upvoting this answer. If this site works, it should slowly make its way to the top of the list. \$\endgroup\$ Commented Aug 3, 2015 at 18:28
  • 1
    \$\begingroup\$ They do the same thing on each metal layer of an IC. In fact for each metal mask you need certain densities (you can have multiple metal masks for the same metal layer). \$\endgroup\$
    – jbord39
    Commented Oct 11, 2016 at 20:48
  • 1
    \$\begingroup\$ Interestingly, I had a 6 layer PCB made and the inner layers also have circular thieving dots applied (it's clearly visible). The inner layer thieving pattern is slightly more tightly packed. Why put them on inner layers, is it to make via plating more consistent? \$\endgroup\$
    – user98663
    Commented Aug 30, 2018 at 12:24
  • 1
    \$\begingroup\$ I know a few LED bar fabs who'd like to have a chat with you about your ideas of "warping is not an issue". It obviously depends on core material but since cheapest possible with some kind of thermal conductivity would be the CEM-1 papier mache PCB which is about as flimsy as you can get.. Perversely you can't put PTH vias on CEM-1 but you still should have "dead" copper on the opposite side. \$\endgroup\$
    – Barleyman
    Commented Aug 30, 2018 at 12:25
  • \$\begingroup\$ Also you might not have to balance copper too much but balancing the components, yes. On most use cases this does not matter but if you're dealing with high density wire-bonding or something, a little bit of warp causes complaints from the cleanroom. \$\endgroup\$
    – Barleyman
    Commented Aug 30, 2018 at 12:30

In general, it is better for the manufacturer when less copper have to be dissolved during the etching process and there is no big continuous areas that need to be etched. It is because of 2 reasons:

  1. Etching more copper means that the etching solutions have to be recycled more frequently - it is an energy and money. An ideal case is if the customer wants a PCB entirely covered with copper. :)

  2. The big solid areas of copper are etched slower than the areas where fine copper pattern is located. That is because the pattern has bigger surface and we know that the chemical reactions speed is bigger if the reaction surface is bigger. This way, after the tracks are already fully etched, the big empty areas are still not, so the PCB have to stay some more time in the solution. This causes some under-etching of the tracks which is not good for the PCB quality because it makes the tracks thinner than intended.


The reaction rate of any etching process is limited by local current densities, access of the reactants into the reaction area and clearance of the reaction products away from the reaction area. Since board etching is essentially a planar or two dimensional process this places further limits on etching performance with reactant delivery and reaction products actively interfering with each other for access to the surface.

While always present in processes, where the problem arises is in the differential etch rates across the board. This can cause thin traces to be etched at a different rate than wider traces. For example, etching a relief from around a fine trace within a background of a ground plane is very different in loading than etching a thin trace with no background ground plane.

This can be corrected for by ensuring that in the design the pattern density remains fairly constant per unit area across the board. Thieving is one way to do this. Some manufacturers will actually place sacrificial elements within the tanks and along side the board to ensure proper yield of different line thicknesses.

Mixing and agitation of the tanks during etch will also help mitigate the differential etch issues.


Thieving might be used for the above exposed purpose (plating, wrapping, etching, etc), for internal layers it has the simple purpose of keeping the PCB thickness uniform across the PCB area. Indeed the PCB manufacturing is using heat press action to stick together the different material layers (core, prepeg, copper, etc).

In order to have the compression force uniform across the area and independent of the material layers you would need to have each layer filled uniformely with material of the same elasticity. But this is not the case because PCB track will be seperated by the prepeg material of the insulator layer. So if you have a large area of an internal layer without copper, the prepeg layer above this copper will need to fill up this empty space.

So if you have areas where layers are empty and other areas filled, the manufacturing process (heat press) will create different pressure across the PCB, creating different thickness across the PCB area. The difference can be significant and it all depends on the thickness of all internal prepeg, hence depending on the copper thickness, PCB thickness and number of layers.

This is why in the picture you provided the large space (too large) is filled.


Thieving is used to balance the current flow density used while plating. It is helpful in situations where there are small traces adjacent to copper pour. The thieving is the process where Electrical Current is diverted to the thieving pads to prevent the burning of the thin trace due to excessive current heating the trace.


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