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I have been reading up on machine code, and in many architectures (x86 IA-32, IA-64, AMD K6, ARM v7, ARM v9) and microarchitectures (Intel Core, P6, P5, etc.) machine code is additionally translated from the source of the RAM itself in to smaller microprograms that do the actual circuit work. However, the microsequencer is what apparently does this. My concern is what is the purpose, why do some microarchitectures not use this, and why do some additionally implement it as well?

Oh, and the main question, most importantly, of course ... how does the microsequencer actually turn electrical signals from RAM in to circuit-level operations correctly?

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  • \$\begingroup\$ A the very least: ask one question per question. The first one is easily answered: different boundary conditions favor different architectures. The second question spans too many abstraction levels to be answered in a short answer. As a start (from the bottom up), you could study how a logical gate (NAND for a start) is build from MOSFETs. \$\endgroup\$ Oct 16, 2013 at 21:44

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To answer your question about how the CPU turns RAM signals into circuit-level operations:

TL;DR

Logic gates.

Full answer

I think an example of what you're asking could be in some ways explained with a decoder, simply because a decoder can "translate" bits of information into something else. In this case, I'll try to explain how a decoder might allow you to access a memory address, based on a 4-bit input.

For example, say you have an 8-bit CPU. The 8 bits could theoretically be divided as so:

1100 | 0001

Where the leftmost bits (1100) represent an operation code, and the rightmost bits (0001) represent a memory address for one of the operands.

Since you allow each memory address to be composed of 4 bits, the largest base-10 number you can have is 16 (1111). And since you are running an 8-bit CPU, you might only be able to run 8 bits at a time through your bus. Thus, you might decide to restrict your RAM to only store 8 bits of information per memory address.

In other words:
16 total memory addresses, with each memory address containing 8 bits.

This gives you a total of 128 bits of memory.

Lets say each address has one input that, when it receives a pulse, will "open" up that address so that the 8 bits of information it holds in a series of 8 latches will be output to the bus.

schematic

simulate this circuit – Schematic created using CircuitLab

In the schematic, there would obviously be RAM 0 - 8, and RAM 11 - 15 to make up your total of 16 registers.

If you study the logic gates, you'll see they're cascaded in a way where any 4-bit input can be turned into only one "enable pulse", which will correspond to the register of that input address.

I would strongly recommend YouTube user madmaxx's playlist Lets Build 8 Bit Computer.

Notes:

The logic gates I've used above accept two inputs. Based on those two inputs, each logic gate will output one signal.

The NOT gate is the triangle with the circle. This one is simple: if the input is 0 (no signal), the output will be 1 (however many volts your signal is, say, 5V).

The AND gate is the bullet-looking symbol. Only if both inputs are 1 (say, 5V), then the output will also be 1. Otherwise, the output will be 0. Here is what's called a "truth table" for the AND gate:

A|B|O
0 0 0
1 0 0
0 1 0
1 1 1

Where A and B are the two inputs, and O is the ouput.

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