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I am trying to route connection on a board. However much I try there is always a via dropped below the IC. It is an SSOP package. IS this okay or is it an issue?

enter image description here

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    \$\begingroup\$ This is normal on professionally fabricated boards, subject to the constraints given in answers. However, if you wanted to make the board yourself without plated through holes, it's all but unworkable, as whatever you run through the via holes to connect the layers would prevent the IC from seating properly. \$\endgroup\$ – Chris Stratton Oct 17 '13 at 15:31
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If by "below" you mean under the IC body, then this is OK (assuming that the package does not have a heat sink pad on the bottom surface). However, it looks like some of your traces are very, very close to the via rings.

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    \$\begingroup\$ Running a DRC with the incorrect clearances set can lead you to believe it is ok - check those distances and check the DRC clearance settings - it looks less than 0.1mm to me. \$\endgroup\$ – Andy aka Oct 17 '13 at 11:34
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    \$\begingroup\$ All the clearances in the clearance settings are 8mil and they said its okay. Also what exactly is close? THe blue is the bottom layer and I see 2 red are placed quite far. \$\endgroup\$ – Developer Android Oct 17 '13 at 11:39
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    \$\begingroup\$ Via's are holes and the tollerance for holes is worse than the tollerance for track to tracks and pads. It's best to ask the Fab by giving them an example like those shown. However, if there is nothing else stopping them from being moved I would move them. Because the effort required is so small compared to the pain of shorts under an IC later... \$\endgroup\$ – Spoon Oct 17 '13 at 12:29
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    \$\begingroup\$ Turn off all of the layers except Top and Vias. Look for the smallest spacing between objects. If that's greater than 8mil and your board vendor allows traces that close to vias then you are fine. Repeat for Bottom and Vias. As s3c said, using the minimum spacing allowed by the board house may give a lower yield than if you increased the minimum widths and spaces by 10% or 20%. \$\endgroup\$ – Joe Hass Oct 17 '13 at 13:34
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    \$\begingroup\$ Also make sure that the IC can have traces routed there; some analog ICs are sensitive to external signals in some places. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 17 '13 at 13:46
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You can place via's anywhere you want however:

If this is a professional made board with plating inside via holes I would recommend 'tenting' these via's. This means that the soldermask is covered over the via so the metal is not exposed. If you don't tent these via's and they are close to solder pins, there is a very big chance solder will stick to this via. This 'short' is really tricky to remove and can take multiple resolder attempts (and a lot of heat/flux/good solder wick) of those pins to remove. Whilst trying to remove the short, you can easily bend of break of a fragile SSOP pin, which is really frustrating I can tell you. ;)

If in doubt: place via's a fair distance (like half to 1 via size) away from the solder pins.

If this is a DIY board, then chances are you create via's by soldering a piece of metal wire on both sides of the board. In that case you usually have a solder joint sticking out under the IC, which means you can't mount the IC flat anymore. Unless you are really careful at trimming down the via solder joint down.

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  • \$\begingroup\$ I plan to give it to a Fab but the components may be soldered by me with the help of a stencil \$\endgroup\$ – Developer Android Oct 18 '13 at 1:18

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