While reading the PPT here (last slide), I found the statement that FPGAs have Deep pipeline parallelism. I have understood the meaning of Deep pipeline parallelism, but can someone explain how actually this is achieved in the FPGA (may be architecture or algorithm point of view) ?
Fundamentally, FPGAs have lots and lots of registers. And lots of tiny RAM blocks also which can be useful for some pipelines.
If you can break down your algorithm into many tiny steps with a register at the end of each step, you can feed in a new data value on each clock tick. During each clock cycle, the whole algorithm is performed, but each part is done on a different "piece" of the input data. After the clock has ticked enough times to cover the number of register stages in your pipeline, the answer for the data which went in that many ticks ago comes out.
Adding register stages to run multiple threads is also called c-slowing.
- Create some pipelined logic that performs a particular function.
- Replicate that logic several times.
- Distribute the input data stream between the logic copies.
- Reassemble the output data from the logic copies into a contiguous output stream.
Ideally, an optimum balance of throughput -v- logic utilisation will be achieved.