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I know now a days FPGAs have very good floating point performance as reported here for example . But then why it is said that Floating point is non-synthesizable in verilog? How FPGA handles float then?

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    \$\begingroup\$ Where is it said that floating point is non-synthesizable in verilog? \$\endgroup\$ – Samuel Oct 18 '13 at 6:03
  • \$\begingroup\$ for example here. They are calling it real. I thing real and float are same. Am I right ? \$\endgroup\$ – gpuguy Oct 18 '13 at 6:08
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    \$\begingroup\$ Real and float are not the same. Reals are, well, real numbers while floating point cannot represent any number like a real can. The answer by apalopohapa explains how to synthesize floating point. \$\endgroup\$ – Samuel Oct 18 '13 at 6:45
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It is not that they can't be synthesized (they can, of course!), but tools won't do it combinationally (like they would a fixed point adder) because the resource usage would be unfeasibly large. So it is done sequentially in multiple steps, and there are many, many ways of doing it with several trade-offs to consider, with division being quite complex. So your floating point operation needs to be treated like any other module, you can design it yourself or license it from a vendor, and a tool won't synthesize c = a/b for you, for the same reasons it won't synthesize an integral or an equation solver, but it doesn't mean it can't be done in an FPGA!

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  • \$\begingroup\$ +1, so you mean the tools only synthesize premitive operations which are easy to optimize? And any complex stuff lkie 3.88 X 89.9898 should be implemented by the designer himself? \$\endgroup\$ – gpuguy Oct 18 '13 at 6:28
  • \$\begingroup\$ See the Xilinx Floating-Point IP core or the Divider. These assist you with implementation but are licensed cores. Also note that modern FPGAs with embedded DSP blocks (e.g. the DSP48A1) can assist with some math operations. \$\endgroup\$ – David Oct 18 '13 at 6:44
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I know you asked about Verilog, but as an adjunct to apalopohapa's answer, VHDL has a synthesisable floating point library, which does not require instantiation of modules to perform floating-point operations, merely the use of ordinary function calls.

Other than the elegant use of VHDL's bit numbering to separate the exponent and significand, I don't think there's anything to stop someone writing a similar set of functions for Verilog to give the same capability.

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