0
\$\begingroup\$

I just learned about SR Latches, D Latches, and their gated versions and I've got a little burning question.

So of course with the SR Latch, the professor told us that the "11" condition cannot occur because the circuit is unstable

enter image description here
(source: kfupm.edu.sa)

Gated D Latch

Then, we learned about the D latch, which has a single input as opposed to 2, and eliminates the "11" condition from ever occurring.

enter image description here

But I realized at this point that in going from 2 inputs t0 1, the D latch also loses the ability to store a value while the clock signal is high because it will always be either "01" or "10" and setting or resetting.

So I was a little confused by that, what if the clock was connected and cycling over and over, and you wanted it to simply store the value? Why not a safe gated SR latch? So I just added some gates to the front to filter out the "11" condition.

So why isn't this used, or is it? Or how do memory elements that use this then store their value when clock is high? Our professor didn't mention this so I'm just curious.

"Safe" Gated SR Latch

enter image description here

animation

Safe Gated SR Latch

\$\endgroup\$
  • \$\begingroup\$ TBH, SR latches and flip-flops are generally only used where both inputs can never be high in the first place (e.g. debouncing SPDT switches). \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 18 '13 at 17:15
1
\$\begingroup\$

The gated D latch is only used in situations where the write-enable (WE) will be pulsed when you want to change the state of the latch. The WE could be generated in various ways for a variety of reasons, but it is probably not a regularly occuring clock signal.

\$\endgroup\$
0
\$\begingroup\$

A more typical arrangement than what you have shown would be to add an extra input to the bottom-left gate, have the "D" input controlled by "set" and the extra input controlled by "reset", or vice versa (reversing the output polarity). In that case, when both set and reset are active simultaneously, one of them (the one which feeds into both of the left-side gates) will win.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.