9
\$\begingroup\$

I want to OR the bits of a vector together. So say I have a vector called example(23 downto 0) and I want to OR all the bits into another vector, is there any way to do this that does not involve going example(0) or example(1) or ...example(23)?

\$\endgroup\$
  • \$\begingroup\$ Could you simply compare to zero instead? That would have the same effect. \$\endgroup\$ – David Oct 19 '13 at 20:50
  • \$\begingroup\$ To expand on David's comment (using a 32 bit vector): or_result <= '0' when input=X"00000000" else '1'; Change the number of zeros to match the length of the vector in question. \$\endgroup\$ – user60166 Dec 10 '14 at 8:18
  • \$\begingroup\$ Logic reduction is available in vhdl 2008, see stackoverflow.com/questions/20296276/… \$\endgroup\$ – Moberg Feb 28 '17 at 12:47
  • \$\begingroup\$ Also you can use more general way: result <= '0' when (example=(example'range=>'0')) else '1'; \$\endgroup\$ – Miguel Risco Apr 16 '17 at 5:06
11
\$\begingroup\$

or_reduce is what you want, and it is available in std_logic_misc. Supported by both A and X for FPGAs.

\$\endgroup\$
  • \$\begingroup\$ and_reduce is the other useful one. \$\endgroup\$ – Aaron D. Marasco Oct 20 '13 at 12:26
3
\$\begingroup\$

Verilog has a convenient "reduction operator" that does exactly what you're asking for: |example[23:0] gives the result of OR'ing all the bits of the example vector.

Unfortunately VHDL doesn't have this operator. According to the comp.lang.vhdl FAQ, though

There is no predefined VHDL operator to perform a reduction operation on all bits of vector (e.g., to "or" all bits of a vector). However, the reduction operators can be easily implemented:

[skipping an example that doesn't handle 'X' and 'Z' values]

    function or_reduce( V: std_logic_vector )
                return std_ulogic is
      variable result: std_ulogic;
    begin
      for i in V'range loop
        if i = V'left then
          result := V(i);
        else
          result := result OR V(i);
        end if;
        exit when result = '1';
      end loop;
      return result;
    end or_reduce;
    ...
    b <= or_reduce( b_vec ); 
\$\endgroup\$
  • \$\begingroup\$ Whoever downvoted, care to explain why? \$\endgroup\$ – The Photon Oct 21 '13 at 2:03
  • \$\begingroup\$ Is this synthesizable? \$\endgroup\$ – Johannes Schaub - litb Aug 3 '17 at 17:06
  • \$\begingroup\$ @JohannesSchaub-litb, of course, it can be synthesized to a really big OR gate (or a tree of smaller ones). Possibly the version in the standard library (in Aaron D. Marasco's answer) will be better optimized than something generated on the fly. \$\endgroup\$ – The Photon Aug 3 '17 at 20:17
  • \$\begingroup\$ VHDL-2008 does have unary reduction operators. The FAQ is outdated. Furthermore, the presented function is of questionable synthesizability because of the early exit which some tools may choke on and isn't necessary other than as a micro-optimization for simulation. \$\endgroup\$ – KevinThibedeau Jan 1 at 3:08

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.