This question is about gate delay in VLSI (microchips). (Yes, it is a CMOS)
Every digital chip consists of 2 kinds of elements, Register Logic (trigger or latch stations) and combination logic (between the registers, does the actual computation). Most chips can be expressed as http://en.wikipedia.org/wiki/Register_transfer_level which describes logic and registers.
The maximal clock frequency of microchip is determined (limited) by the delay of the slowest combination path. This delay depends from kind of elements, used in it.
The most popular metric of this critical delay is FO4 http://en.wikipedia.org/wiki/FO4 or Fan-out of 4:
process independent delay metric used in digital CMOS technologies.
It is counted as chain of length N of NOT gates. Each gate have output power enough to drive 4-fold more powerful inverter (according to wiki). I get this metric as tree of inverters with N levels, where each inverter drives 4 same inverters. Tree looks like http://www.mathworks.com/help/toolbox/wavelet/ug/wptreed2.gif but with NOT gates (transistors) at nodes. (better description is at http://www.realworldtech.com/page.cfm?ArticleID=RWT081502231107 )
So, the any modern processor have a metric FO4, which can be equal to 14, or 20 or 40. If the processor have small FO4, it can have more frequency, than a processor with large FO4 at the same silicon technology.
I have a metric for critical path of some chip, expressed in terms of fan-in-2 and fan-out-3:
18 fan-in-2 fan-out-3 NAND gates
How can I convert this to FO4? (Fan-out of 4)
I want to compare this chip with modern CPUs. FO4 will give me a clear way to check, how fast the chip can be on technology of modern CPU.
Update: There is a book which says:
This fan-out-of-four (FO4) inverter delay, t_4, is a good estimate of the delay of typical logic gate (fan-in=2) driving a typical load (fan-out=2) over relatively short wires.
So, Fan-in=2 and Fan-out=3 is close to 2/2 or to FO4. For the first estimation I will use this 18 fi2/fo3 as equal to 18 FO4.