Convert fan-in-2 fan-out-3 NAND gates to FO4

Question

This question is about gate delay in VLSI (microchips). (Yes, it is a CMOS)

Every digital chip consists of 2 kinds of elements, Register Logic (trigger or latch stations) and combination logic (between the registers, does the actual computation). Most chips can be expressed as http://en.wikipedia.org/wiki/Register_transfer_level which describes logic and registers.

The maximal clock frequency of microchip is determined (limited) by the delay of the slowest combination path. This delay depends from kind of elements, used in it.

The most popular metric of this critical delay is FO4 http://en.wikipedia.org/wiki/FO4 or Fan-out of 4:

process independent delay metric used in digital CMOS technologies.

It is counted as chain of length N of NOT gates. Each gate have output power enough to drive 4-fold more powerful inverter (according to wiki). I get this metric as tree of inverters with N levels, where each inverter drives 4 same inverters. Tree looks like http://www.mathworks.com/help/toolbox/wavelet/ug/wptreed2.gif but with NOT gates (transistors) at nodes. (better description is at http://www.realworldtech.com/page.cfm?ArticleID=RWT081502231107 )

So, the any modern processor have a metric FO4, which can be equal to 14, or 20 or 40. If the processor have small FO4, it can have more frequency, than a processor with large FO4 at the same silicon technology.

I have a metric for critical path of some chip, expressed in terms of fan-in-2 and fan-out-3:

18 fan-in-2 fan-out-3 NAND gates

How can I convert this to FO4? (Fan-out of 4)

I want to compare this chip with modern CPUs. FO4 will give me a clear way to check, how fast the chip can be on technology of modern CPU.

Update: There is a book which says:

This fan-out-of-four (FO4) inverter delay, t_4, is a good estimate of the delay of typical logic gate (fan-in=2) driving a typical load (fan-out=2) over relatively short wires.

So, Fan-in=2 and Fan-out=3 is close to 2/2 or to FO4. For the first estimation I will use this 18 fi2/fo3 as equal to 18 FO4.

Answer 1

According to David Harris's presentation for eve224a course: (slides 6-11 and 47)

Delay d = f+p = g*h+p

Where d is process-independent delay, f is effort delay (stage effect), p is parasitic delay, g is logical effort, h is electrical effort (fanout; h = C_out/C_in)

In the Wikipedia article "Logical Effort" there are some examples too:

Delay in an inverter. By definition, the logical effort g of an inverter is 1

Delay in NAND and NOR gates. The logical effort of a two-input NAND gate is calculated to be g = 4/3

For NOT gate with FO1 (driving the same NOT gate):

g=1; h=1; p=1; so d = 1*1 + 1 = 2

For NOT gate with FO4 (the FO4 metric itself):

g=1; h=4 (Cout is 4 times more than Cin); p=1 so d = 1*4+1 =5 (the same result is at page 20 of books "Logical Effort: Designing Fast CMOS Circuits", draft from 1998)

1 FO4 delay is equal to 5 process-independent units (defined by harris, slide 6)

For NAND gate with two inputs (p=2) which drives the same:

g=4/3; h=1; p=2; d= 4/3 * 1 + 2 = 10/3 = 3,3 (a 1.5 times slower than NOT with FO1, but faster than NOT FO4)

For NAND gate asked by me - 2 inputs which drives 3 same NANDs:

g=4/3; h=3; p=2; d= (some magic inside) 4/3 * 3 + 2 = 6

So

Delay of 1 FO4 gate is equal to 5/6 delay of NAND (2-in, 3 FO).

The last problem is to convert chain delay of 18 NANDs to chain delay of FO4. (slide 41 of harris)

Hmm.. seems I need only to multiply 18 NANDs delay with 6/5... 21,6 FO4.

Thanks!

Answer 2

Unfortunately, I would say it's impossible to have a formula.

FO4 delay consists of

1) Charging time of your invertor input capacitance

2) Invertor transition time

3) Charging time of your invertor output capacitance

When going from FO2 to FO4 there are different factors on each of these items, specifically, 1 and 3 going to be about twice slower, but 2 is going to be just a little bit slower (as channel length is more or less the same).

On your place I would try to resimulate FO4 circuit for your tech.process and see simulated delay.