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The explanation of a PLL is here, for a PLL, what is the meaning of the following terms?

  1. Capture Range ?
  2. Lock Range ?

What is it about the PLL circuit that might have these two terms span a different range. Or are they always the same?

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    \$\begingroup\$ This question appears to be off-topic because it indicates a lack of effort. \$\endgroup\$ – Anindo Ghosh Oct 21 '13 at 14:30
  • \$\begingroup\$ Edited this question to fit what might be an acceptable way of posting a question here. If you disagree, just rollback the edit. \$\endgroup\$ – placeholder Oct 21 '13 at 14:55
  • \$\begingroup\$ @AnindoGhosh either way, briefly explaining terms or vocabulary of electrical engineering here is productive, rather than relying on external resources. \$\endgroup\$ – Iancovici Oct 21 '13 at 14:57
  • \$\begingroup\$ @echad I agree. The end, however, ought not justify the means, to wit, copy-pasting a set of terms into a list and calling it a question. \$\endgroup\$ – Anindo Ghosh Oct 21 '13 at 15:06
  • \$\begingroup\$ @Anindo: Lack of effort is grounds for downvoting, not for being off topic. While I agree the question is lazy and exhibits no research effort, it is squarely on topic. \$\endgroup\$ – Olin Lathrop Oct 21 '13 at 17:59
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There is much out there on the basic descripton of a phase-locked loop (PLL). Basically, a PLL is a phase comparator producing a feedback signal to adjust a independent oscillator to exactly match the frequency of some incoming signal. The output of the oscillator then is a locally produced copy of the incoming signal. That by itself may not sound useful, but here are some things that can be done with this:

  1. A little low pass filtering of the oscillator control signal can make the local signal be a "cleaned up" version of the incoming signal.

  2. It is a way of making a low impedance version of a incoming clock without clock skew. This is useful for distribution of high speed clocks. If you just took the incoming weak clock signal and ran it thru some gates to clean it up and distribute it, you would get delay in those gates, hence clock skew.

  3. You can put a frequency divider between the oscillator and the phase comparator. The PLL then becomes a frequency multiplier, since the oscillator must be running at the divide value times the incoming frequency.

  4. The oscillator frequency adjust input signal can be useful. This is one way of doing FM demodulation, for example.

Capture range and lock range refer to how close the local oscillator frequency needs to be to lock onto the incoming signal. Since the phase comparator goes thru its full output range over only 1 cycle of mismatch between the incoming signal and the local oscillator, it's output becomes effectively gibberish when the frequency difference is high. It goes back and forth so fast that the local oscillator doesn't have enough time to adjust.

The capture range is the incoming signal frequency range over which the phase comparator and oscillator can react fast enough so that phase lock is achieved before the phase comparator goes thru another cycle. This is basically what the input frequency needs to be for a cold start.

Tracking range is the range of input frequencies over which the oscillator can stay in lock once lock was achieved. This is a wider range than the capture range since the comparator is already in lock, so incoming frequency variations are dealt with incrementally.

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  • \$\begingroup\$ Is there a term for the range of frequencies within which the output of a PLL is guaranteed to stay within no matter what the input signal does (including in non-locked conditions)? Such a range (especially its high end) is often important when a PLL is used to drive something like a processor clock, but I don't know a term for it. \$\endgroup\$ – supercat Oct 21 '13 at 16:17
  • \$\begingroup\$ @supercat: I don't either. \$\endgroup\$ – Olin Lathrop Oct 21 '13 at 17:58
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A typical PLL will have an oscillator circuit that can output some range of frequencies in response to a control voltage, along with a circuit that will try to very the control voltage fed to the oscillator so as to make its output match a reference. While PLL behaviors can be very complex, it is sometimes useful to summarize their behavior with a few values:

  • A range of frequencies that the oscillator is guaranteed to always stay within, regardless of what the PLL's reference input is doing. Knowing this range may be important if the PLL is driving a device (like a processor's clock input) whose frequency must never go outside a certain range whether the PLL is locked or not.

  • A "capture range" of possible reference frequencies such that if the reference remains stable at a particular frequency for a particular length of time, there is an extremely high probability that the PLL will lock within a certain tolerance. Note that--quantum-mechanical effects aside--it's impossible to design a PLL which won't fail to lock under some exact combination of stimuli even within the capture range.

  • A "tracking" range of reference frequencies within which the reference may "slowly" (relative to the PLL frequency) drift without causing the PLL to lose an established lock.

Note that in some cases it may be useful to have a guarantee that a PLL will fall out of lock if the reference goes beyond a certain range; when trying to receive an FM signal in a crowded band, for example, if a weak signal from channel of interest reaches the low point of its modulation just as a strong signal from the channel below reaches the high point, the frequencies may be close enough that the PLL might erroneously lock onto the stronger signal. It would be helpful to guarantee that if that happens the PLL will fall out of lock when the frequency of that strong signal swings down again (thus giving the PLL a chance to lock onto the right frequency).

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