# pipeline and verilog

I am having a pipelined scheme and I want to have a register at the output for my result.

So, I am using this code:

 always @(posedge clk, posedge reset) begin
if (reset) begin
//do staff
end else begin
if (state_5) begin
output <= ....
end
end
end


however for timing reasons, I want the result to be available on the same cycle. If I change my code to this:

always @(posedge clk, posedge reset) begin
if (reset) begin
//do staff
end else begin
if (state_5) begin
output = ....
end
end
end


results are available in the next cycle as well.

If I change into that:

always @(*) begin
if (state_5) begin
output = ....
end
end


I am ok with timing. My question is , does this code infers a register to be used?

my output is defined as output reg.

• An inferred latch is definitely not the same thing as a pipeline register. – Dave Tweed Oct 21 '13 at 16:32

## 2 Answers

Your first example will definitely infer a register, and the output will be available after all the <= statements in the always block are executed. The second example will most probably infer a register (I'd also expect at least a warning, or an error here, depending on your synthesizer). The block will execute only with sensitivity to clk and reset signals, and thus, the synthesizer should infer a register.

The third example will NOT infer a register, since the output will be sensitive to all of the signals in the always block (those that constitute the formation of the output signal as well.) This means that, the circuit here is not clock triggered, thus not a register but a latch. As Dave Tweed's comment mentions, a latch is definitely not the same thing as a pipeline register.

So, the correct way (as far as I know) to use this is to divide your code up into two pieces, one bit the combinational logic, and one bit for the sequential logic. It'd look something like:

reg out_r;
wire out_c;

assign out_c = ... ;

always @(posedge clk, posedge rst) begin
if(reset) begin
...
end else begin
out_r <= out_c;
end
end


Anything that follows the always @(*) if(condition) reg_type=value; will infer a latch. You most likely do not want to have a latch.

If you want the result quickly, then you can separate the combination logic from the synchronous logic.

always @(*) begin
// set default : acts as a catch-all else statement. No latch is inferred.
next_out = out;
if (state_5) begin
next_out = ....
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
// reset stuff;
end
else begin
out <= next_out;
end
end


Just remember there is still propagation delay.

Note: output is a Verilog keyword. Make sure you use a different name, such as out, output_reg, or something more descriptive.