# Buck converter with feedback loop

According to this site in a buck converter with voltage mode control the duty cycle is set directly by comparing a voltage ramp to an error voltage. I agree with that. But this is where my headache starts:

If Vo < Vref, then Ierr is positive - increase V(10) and the PWM duty cycle.

If Vo > Vref, then Ierr is negative - decrease V(10) and the PWM duty cycle.

If Vo ~ Vref, then Ierr is close to zero - maintain V(10) and the PWM duty cycle

where Vo is the output voltage and Vref is the reference voltage. Well, the first two lines are ok for me, but i can't imagine how the duty cycle is maintained, when Vo ~ Vref.

My assumption here is, that when Vo ~ Vref holds, then the duty cycle should be set to 50% and not maintained. Or am i missing something here?

Regards

Macs

When Vo is not the correct value (Ierr != 0) the duty cycle has to be adjusted. If Vo approaches Vref the adjustments become smaller until there's the point where Vo = Vref, and no adjustments are necessary anymore. If you would change the duty cycle to 50% at that point, Vo will no longer be equal to Vref.
Besides, if your duty cycle would always be 50% for the correct Vo, then there wouldn't be any regulation, would it? You would just set it to 50, and that would be that.

• Yes it would, but from the given circuit on the webpage i don't unterstand "how" the duty cycle is held in a steady state. My thoughts are like this: The OTA compares Vo and Vref, when they are equal the current Ierr = 0, right? Then the positive input of the comparator is also 0 and when i compare that to the voltage ramp i get a different duty cycle. Jan 5, 2011 at 16:50
• Well i think i'm having an error in reasioning, because Vo = Vref can only be achieved, if the duty cycle is set correct. Jan 5, 2011 at 17:09

A buck duty cycle is fundamentally defined by Vout / Vin. If you have 12V in and 5V out, 5 / 12 ~= 0.416 which is 41.6 percent.

The error amplifier compares a sample of the output voltage (usually with some frequency compensation) to a fixed, precise reference voltage. This is what is referred to as the error signal.

If the output voltage goes high for some reason, the error signal will cause the PWM to reduce duty cycle in an attempt to bring the error to zero.

If the output voltage goes low for some reason, the error signal will cause the PWM to increase duty cycle in an attempt to bring the error to zero.

If the output voltage matches the reference voltage, the duty cycle will be as per the above formula (which is a first-order approximation; losses and delays will add some extra duty cycle to the result.)

The Duty Cycle of a buck converter is D = t_on / T = V_out / V_in.

This (and not 50 %) is the ratio that has to be maintained once things are up and running.

What you set is the sample of the output voltage in relation to the reference voltage (via the resistive divider). From then on, the control loop will maintain the duty cycle such that the output will stay in regulation.

It will be very hard (or plain impossible) to set the duty cycle by using a function generator, even one with a crystal clock, with the great precision that would be required in order to not have the output drift somewhere because you would have to take care of all the tiny parasitics in your circuit. With a control loop, all that stuff can be taken care of and maintained easily.