According to this site in a buck converter with voltage mode control the duty cycle is set directly by comparing a voltage ramp to an error voltage. I agree with that. But this is where my headache starts:
If Vo < Vref, then Ierr is positive - increase V(10) and the PWM duty cycle.
If Vo > Vref, then Ierr is negative - decrease V(10) and the PWM duty cycle.
If Vo ~ Vref, then Ierr is close to zero - maintain V(10) and the PWM duty cycle
where Vo is the output voltage and Vref is the reference voltage. Well, the first two lines are ok for me, but i can't imagine how the duty cycle is maintained, when Vo ~ Vref.
My assumption here is, that when Vo ~ Vref holds, then the duty cycle should be set to 50% and not maintained. Or am i missing something here?