I have an analog to digital converter that reads in and sends data out on falling edges. I also have two MCU's the FEZ Hydra and the FEZ Cobra. I've noticed using the oscilloscope that the data into the ADC and the data out of the ADC is exactly the same, however when reading the data on the computer that the MCU's have stored I get different values.

Since the ADC only sends outputs on falling clock edges, whenever the data output bits change from a 0 to 1 the Hydra reads in a 1 while the cobra still reads in a 0; and whenever the data output bits change from a 1 to 0 the Hydra reads in a 0 and the cobra still reads in a 1. It seems like the Cobra doesn't give enough time between the negative clock edge and reading of the input to allow for the update to happen.

I am using microsoft's spi library. My question is: Is there anyway for me to delay the SPI read function? What is the reasonable output in this situation supposed to me?

Note: There is a 60ns delay on data access time on the ADC.

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2 Answers 2


SPI peripherals have the ability to select the clock polarity and phase with respect to the data, so you need to make sure the data is being read on the correct edge. It looks as if the two uC's have differing phase. The SPI Wiki page (and any other half decent SPI tutorial) has details:


I'm not sure how you set things up with your hardware, but the relevant settings shouldn't be too hard to find.

  • \$\begingroup\$ The ADC reads AND sends data at every falling edge how can I use either of these schemes since data is being captured and propagated on the same edge. Currently I use a high clock idle state CPOL = 1 and my timing diagram matches with the red line of CPHA 1 even though the red line belongs to CPHA 0. \$\endgroup\$ Commented Oct 24, 2013 at 20:16
  • \$\begingroup\$ @user1084113 I may be being stupid but why not add an inverter to the clock signal going to the ADC. The cobra and hydra will still read differently (now reversed) but without getting into the ins and outs of cobra & hydra to find out why one or the other reads data on the "opposite" edge you may not have any choice. \$\endgroup\$
    – Andy aka
    Commented Oct 24, 2013 at 20:51

I would agree with the prior answer. SPI peripherals generally have two bits somewhere in the control registers. These are called clock phase (as already mentioned) and clock polarity. Clock phase determines, whether data is sampled on the rising or falling edge of SCK. Clock polarity only determines SCK's state in-between byte transfers (some devices don't care about this option).

From your explanation, I am not quite sure whether you setup OR sample your data on the falling or rising edge. Seeing that you have drawn a picture with lines on falling edges of the signal, I suppose you want your devices to sample (read) the value on that very edge. That is rather unconventional. Also, it is in contradiction with your picture.

The bus works like this.

  • setup the value on one edge of SCK
  • sample it on the other

Usually, setup is done on falling, and sample on rising.

In the end, fixing your clock polarity and/or clock phase will very likely fix your problem.

  • \$\begingroup\$ Usually, setup is done on falling, and sample on rising, this is the problem this ADC does setup on the falling and also sends data out on the falling edge \$\endgroup\$ Commented Oct 25, 2013 at 14:40

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