Well I got the following (multiple choice) question. Even with the result given I have 0 idea how they could come to the conclusion..

With 64 memory elements of size 1Mx4 and several 2-input decoder chips an as large as possible memory system with words of 16 bits is being built.
How many decoder chips are needed for this system?

From what I understand this means you have a total of 64 * 1M * 4 = 256M bits memory. Which have to divided into words of 16 bits, so 16M addressable locations. This means that the memory-adress-size needs to be at least 24 bits. (So far it is correct right?)

To access it there are 2-input decoder chips (so 4-outputs on each chip). These can be build like a tree to allow for more bits of adresses. Now the problem is, this easily gets very large.

The answer that was correct was "5".
I have no idea how that answer is found: a sytem with 5 2 input decoders consists of 2 layers, and has 16-output lines. What do I understand wrongly here?


1 Answer 1

  1. You have 64 memory elements, and you need them 4 wide (because 16b/4b=4). You therefore have 16 banks to switch between.

  2. You have a 24-bit address space, and devices with 20 address bits. 24-20=4, and 2**4=16.

  • \$\begingroup\$ "You have a 24-bit address space, and devices with 20 address bits." Huh how do I have devices with 20 address bits already? \$\endgroup\$
    – paul23
    Oct 27, 2013 at 18:29
  • \$\begingroup\$ @paul23: Your question claims that you have 1Mx4 devices. \$\endgroup\$ Oct 27, 2013 at 18:31
  • \$\begingroup\$ Still working this out - so if the question said you have "1024Kx4" devices it would've been different things? - Then the device would have 10 address bits? (So you conclude this from the "M")? - Really annoying as my prof has not told anything about these memory notations, and can't find it in the book either. \$\endgroup\$
    – paul23
    Oct 27, 2013 at 20:11
  • \$\begingroup\$ @paul23: en.wikipedia.org/wiki/… \$\endgroup\$ Oct 27, 2013 at 21:51

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