Well I got the following (multiple choice) question. Even with the result given I have 0 idea how they could come to the conclusion..
With 64 memory elements of size 1Mx4 and several 2-input decoder chips an as large as possible memory system with words of 16 bits is being built.
How many decoder chips are needed for this system?
From what I understand this means you have a total of 64 * 1M * 4 = 256M bits memory. Which have to divided into words of 16 bits, so 16M addressable locations. This means that the memory-adress-size needs to be at least 24 bits. (So far it is correct right?)
To access it there are 2-input decoder chips (so 4-outputs on each chip). These can be build like a tree to allow for more bits of adresses. Now the problem is, this easily gets very large.
The answer that was correct was "5".
I have no idea how that answer is found: a sytem with 5 2 input decoders consists of 2 layers, and has 16-output lines. What do I understand wrongly here?