TLDR: The specific ordering question I'm asking is:
- Suppose the output depends on some intermediate signals
- Suppose the intermediate signals depend on some input signals
- Suppose an input signal changes
- This may make more than one intermediate signal change
- The timing of signal assignment is not stringently specified
- If the output signal generation function observes one of the intermediate signals as having changed before the other intermediate signals having changed, a "transient" output may be generated until the change in the second intermediate signal is observed.
- Does VHDL guarantee that this does not happen? If so, how?
Reading through the Free Range VHDL book, on page 37, there is a code snippet that is claimed to be equivalent to the code snippet on page 36:
-- library declaration library IEEE; use IEEE.std_logic_1164.all; -- entity entity my_ckt_f3 is port ( L,M,N : in std_logic; F3 : out std_logic); end my_ckt_f3; -- architecture architecture f3_2 of my_ckt_f3 is begin F3<=((NOT L)AND(NOT M)AND N)OR(L AND M); end f3_2;
-- library declaration library IEEE; use IEEE.std_logic_1164.all; -- entity entity my_ckt_f3 is port ( L,M,N : in std_logic; F3 : out std_logic); end my_ckt_f3; -- architecture architecture f3_1 of my_ckt_f3 is signal A1, A2 : std_logic; -- intermediate signals begin A1 <= ((NOT L) AND (NOT M) AND N); A2 <= L AND M; F3 <= A1 OR A2; end f3_1;
But! The description in the text claims that signals are delayed assignment ("some time" after) and timing or ordering is not guaranteed.
In my mind, this translates to approximately something like "the right side is sampled on clock-rising, and the left side is written on clock-falling," although I'm sure different implementations are actually used in reality.
Now, assuming that each <= operator in a logic chain introduces a time delay of undetermined amount, why are these two snippets equivalent? Couldn't it be that the second implementation, with temporary signals, temporarily outputs some logic value that is not actually the result of any combination of the inputs that it has seen?
I guess I'd like a more formal understanding of what the "signal assignment" really means for timing and outputs. Are compilers guaranteed to "optimize" or "short circuit" temporary signal assignments so that the end result will always be the same as if I wrote the logic expression on a single line?