I'm a new Eagle user and I created an SOIC part with a small heat pad in the middle. The pad is on the bottom and at the top copper layers. The bottom pad is purely for soldering convenience sake. Its easy to solder the pad by heating the bottom pad with your soldering iron.

The board has 2 layers and the bottom one is all GND. I've attached an image here.

The manufacturer says that I should extend the heat pad beyond the IC and put some vias so that heat is transferred to a larger plane. I've put these vias and named them GND but I keep getting an "Overlap" error. Why is this?

Also all the copper pours are created with zero widths because it gave me better control over the fill and now I get "Width errors". How do I resolve these?

eagle overlap errors

  • \$\begingroup\$ If you're assembling this board with an iron (rather than reflow), then you're really going to need thermal relief on all of your passive component pads, too. \$\endgroup\$ – Dave Tweed Oct 30 '13 at 13:40
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    \$\begingroup\$ Also, you should know that vias-in-pads are OK for hand assembly, but if you ever intend to have this board mass-produced, they will require extra manufacturing steps to fill/plug them prior to reflow soldering. Otherwise, they tend to "wick" the solder away from the intended joint. \$\endgroup\$ – Dave Tweed Oct 30 '13 at 13:45
  • \$\begingroup\$ Thanks Dave. Yes I realized that the fills need to have thermal reliefs. \$\endgroup\$ – hpb Oct 30 '13 at 13:57

There is a DRC option (Clearence -> Same Signals -> SMD-VIA) that checks the distance between VIAs and SMD pads, even if they connect to the same signal. This is probably the reason why you get the OVERLAP error.
As a workaround you could just set this restriction to 0. But you should consider placing the VIAs within your package design, since the DRC will ignore the minimum distance rule in that case.


I also have overlap errors in my PCB BUT it's because I didn't use .sch to create .brd ( pcb "drawn" directly by placing parts and connecting of pads) BUT all SMD components (resistors/capacitors in 0805 and 1206 and few SOT-23 transistors) soldering pads get overlap errors because nets are simply going "trough" (over) them, there is just "optical" connection but with command "move" a can move those SMD parts around without moving nets that should be attached to corresponding pads.

I know that if I did used first .sch than there would be those yellow " unrouted " lines around those smd parts, well those yellow one ARE connected on those pads just as my bottom layer nets should be, but even when I chose finest visible grid ( 0.00025 inch) and full zoom I simply can't get my bottom layer (16) "wire" on same place where yellow "Unrouted layer (19) begins to make real connection. sorry bcs my english :)

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    \$\begingroup\$ Welcome to EE.SE! However, it doesn't seem like your answer really addresses the original question. It sounds like you are talking about a different problem altogether, but you already know why you had the problem so you aren't asking a new question either. This post should have been a comment to the original question rather than entered as an answer. \$\endgroup\$ – Joe Hass Jan 16 '14 at 0:19

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