5
\$\begingroup\$

We are currently designing a large PCB where multiple engineers are contributing to the schematic layouts in Altium Designer 13. We decided to use a hierarchical layout for our design so that each engineer works independently on their sub-system to be integrated in a top sheet at a later stage.

In order to keep things neat we tend to use a lot of harnesses in our schematics. This has been causing some problems when running ERC checks on the schematic. In general we tend to pass a harness to a lower sheet through a sheet entry, extract the contents of the harness (using another harness creator), and connect the extracted elements to their respective locations using net-names. The problem is that this tend to cause multiple names to be assigned to the elements of the harness. For example, if a harness called H has elements A and B we tend to connect the net name A and B to the elements when we extract or create the harness. Altium however names the elements H.A and H.B when using a harness with these elements. This causes an error (or warning) for multiple net names if that option is selected in the ERC. Is there an easy way around this behaviour or should we be drawing our schematics in a different manner?

We do not want to disable the multiple net names warning/error as this has previously helped us to find a few bugs. Also I know we can extract the elements by explicitly using the H.A and H.B syntax in the sheets but it is usually quite helpful to visually see on the sheet what all the elements of a harness are.

What I would like to see is that there is an option so that the multiple net name checker takes H.A and A as being equivalent for net name purposes. Currently we have to step through all the warnings and explicitly assign an ERC ignore cross for each net that causes this behavior.

\$\endgroup\$
  • 2
    \$\begingroup\$ Why don't you just name them H.A and H.B. This is especially useful when you're dealing with e.g. multiple SPI interfaces. You will get SPI0.SCK, SPI0.NCS0, ... and SP1.SCK, SP1.NCS0 and so on. \$\endgroup\$ – Tom L. Oct 30 '13 at 18:33
  • \$\begingroup\$ That is certainly something we are considering. The net names does tend to get very long for many signals though reducing the readability of the sheets a bit (personal opinion). For example having pwr_feedback.n_pwr_seq_done lying around can become a bit verbose. I was hoping there was an elegant way to get around the problem but I would understand if this was an design decision on Altium's part. \$\endgroup\$ – Neville Bamshoe Oct 31 '13 at 6:58
  • \$\begingroup\$ Have you tried Net Tie component type? \$\endgroup\$ – PF4Public Dec 27 '14 at 20:40
3
\$\begingroup\$

The best way to do this in Altium is to use Net Ties. These will join two separate nets. See: https://www.smtnet.com/library/files/upload/NetTies-and-How-to-Use-Them.pdf

I will also occasionally use zero-ohm resistors to accomplish the same goal if there is a chance that I may need to break the connection to help troubleshoot an issue.

\$\endgroup\$
0
\$\begingroup\$

If you clear all net names on harness(for example harness: "BUS") on top level sheet. Then this warning message with multiple net names BUS.DATA0 / DATA0 disappear. (There is necessary to have clear harness lines without harness names. Then is no multiple net names warning for lines in harness.)

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.