We are currently designing a large PCB where multiple engineers are contributing to the schematic layouts in Altium Designer 13. We decided to use a hierarchical layout for our design so that each engineer works independently on their sub-system to be integrated in a top sheet at a later stage.
In order to keep things neat we tend to use a lot of harnesses in our schematics. This has been causing some problems when running ERC checks on the schematic. In general we tend to pass a harness to a lower sheet through a sheet entry, extract the contents of the harness (using another harness creator), and connect the extracted elements to their respective locations using net-names. The problem is that this tend to cause multiple names to be assigned to the elements of the harness. For example, if a harness called H has elements A and B we tend to connect the net name A and B to the elements when we extract or create the harness. Altium however names the elements H.A and H.B when using a harness with these elements. This causes an error (or warning) for multiple net names if that option is selected in the ERC. Is there an easy way around this behaviour or should we be drawing our schematics in a different manner?
We do not want to disable the multiple net names warning/error as this has previously helped us to find a few bugs. Also I know we can extract the elements by explicitly using the H.A and H.B syntax in the sheets but it is usually quite helpful to visually see on the sheet what all the elements of a harness are.
What I would like to see is that there is an option so that the multiple net name checker takes H.A and A as being equivalent for net name purposes. Currently we have to step through all the warnings and explicitly assign an ERC ignore cross for each net that causes this behavior.