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I have been doing a project involving partial reconfiguration of a FPGA for some time now. I am having trouble understanding what is meant by terms like 'partial bit file', 'bitstream' etc. How can a .bit file be partial? Also, I know Xilinx provides PlanAhead tool for reconfiguration, but does it require some sort of license to get it working? I know that for reconfiguration, I would have to separate my fabric into two parts-static and dynamic. While static part is what is usually done, is there a specific way to code my dynamic logic in HDL? Any help would be appreciated! Thanks!

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The idea behind partial reconfiguration is that you can basically swap out a portion of your design on the fly without having to reconfigure the entire FPGA. I have not used partial reconfiguration myself, however. And you may need the System Edition of ISE to get access to PlanAhead.

The bitstream is the configuration information that informs the FPGA how to configure all of its interal logic and routing elements and block RAMs to implement your design. The idea with partial reconfiguration is you don't specify a configuration for the entire FPGA, just for some portion of it. There are certainly limitations on how much of the chip can be reconfigured on the fly and how the reconfigurable portion needs to interface with the rest of the design.

As far as how to code the dynamic portion, well, it's not really 'dynamic' per se, just reconfigurable. So you would have to generate probably a separate project for each configuration, and each project would have the implementation of that configuration. The outputs of those would be partial bit files. When you load one of the partial bit files, it would replace the implementation of the configurable block accordingly.

Let's say you had a design for a software defined radio that can speak several different wireless standards. You can have a common interface to the data path and ADCs and DACs and maybe even a softcore or two in the non-reconfigurable part. Then you implement the specific modems in the reconfigurable section. On the fly, you can load up a partial bit file and shut down the radio and swap out the modem while the softcores are still running.

I'm afraid I can't be of much help on the specifics, though, as I have no experience with partial reconfiguration.

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Just a brief expansion on Alex's answer. The tool flow he describes is the one suggested by Xilinx, which is probably where you should start. However, as long as you can generate partial bitstreams you can run-time reconfigure the FPGA at will. The restrictions Xilinx places on partial run-time reconfiguration are more related to their tools than what the FPGA hardware is capable of.

Our research group has been working on implementing Dynamic Circuit Specialization, which generates new specialized circuits at run-time and updates the FPGA configuration to fit the new circuit. It is useful when the number of possible modules is very large, for example when implementing a adaptable FIR-filter. If you are interested in this, our tool flow can be found on github.

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