In the old designs of data communication there was a capacitor to reduce the slew rate of a data communication line. But these days there is a some module called 'on chip slew rate limiter' circuit configuration that does exists independent from it's cable length or the cable characteristics. How does that driver work? What's the mechanism behind that?
Is that they use a microprocessor to calculate the dynamic transfer function of the medium so that they could switch between internal capacitors , is that how it work?