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In the old designs of data communication there was a capacitor to reduce the slew rate of a data communication line. But these days there is a some module called 'on chip slew rate limiter' circuit configuration that does exists independent from it's cable length or the cable characteristics. How does that driver work? What's the mechanism behind that?

Is that they use a microprocessor to calculate the dynamic transfer function of the medium so that they could switch between internal capacitors , is that how it work?

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  • \$\begingroup\$ You're going to have to give explicit examples there are so many different ways that is this accomplished/used that as posed this is question is overly general. \$\endgroup\$ – placeholder Nov 4 '13 at 3:54
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What chip are you talking about here, exactly?

I'm not sure how it's implemented in all cases, but I highly doubt anything is done with transfer functions. My guess is they use some sort of adjustable current driver configuration, possibly with multiple stages. I think a good solution would be to have an adjustable current limited stage followed by a voltage follower, possibly also with adjustable current. Xilinx FPGAs allow three different slew rate selections and several different drive current selections, so it seems like they may be using something along these lines. For other chips, I'm not really sure what the implementation might look like.

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