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According to Xilinx FPGA product datasheets, the numbers on the 5th line as 4C or 5I stand for speed grade and temperature.I have a XC3S400 with 4C speed grade (4= standard speed, 5= High performance).

I want to know what exactly the standard speed grade means ? Can I relate it to a specific bandwidth? For example assume I want to make a high speed counter and want to use the maximum possible speed driven from a crystal oscillator into GCKx pins. Can I use this 4C marking as a guide for crystal oscillator selection?

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The speed grade has to do mostly with specified transistor switching speed. You can review the definition of -MIN, -4 and -5 speed grades in appnote 312, page 125 onwards.

This determines how quickly you can run internal clocked circuits. It will not influence the choice of your crystal oscillator, as you will use a PLL multiplier to generate the actual system clock from a realistic crystal frequency.

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The answer of the user36129 is pretty accurate, but in many cases, specially in the low cost FPGAs, the devices with the high performance are the one taken out of each batch after they prove to be faster than the "standard" defined on the specification of the device. Different companies have different ways of doing this, but I believe Xilinx tests ever single device after production and then sorts them out based on the performance they show during the test. Other companies do sample test on each wafer and if all the samples proven to be fast, then they mark all those devices in that batch for high performance.

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    \$\begingroup\$ Addendum to this answer: this way of selecting parts and putting different 'grade' markings on them even though they are exactly the same silicon design is called 'binning'. \$\endgroup\$ – user36129 Nov 7 '13 at 13:29
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    \$\begingroup\$ This testing is also a large part of why FPGAs are so expensive - every bit in every block RAM, every LUT, every configuration of every transceiver, every IOB, and every routing matrix switch is tested to ensure that the entire FPGA will peform up to spec. This testing takes time for each FPGA, and time is money, so that becomes part of the price of the chip. \$\endgroup\$ – alex.forencich Dec 5 '13 at 2:05
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Speed grades used to correlate with a measurable element (IIRC it was the delay through a look-up table, so a -1 part had a 1ns delay).

That started to get daft for two reasons:

  • LUTs got faster than 1 ns
  • Routing started to play a much bigger role in the performance.
  • That's not the only performance parameter that you are interested in, especially once Block RAMs, multipliers and DSP elements etc come in to play.

So the manufacturers decided to just choose a more arbitrary scheme where each number represents a set of timing parameters (which you can see in the datasheet) and bigger numbers are faster (and more expensive :)

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