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The following circuit from a textbook models an inverter implemented by a MOSFET switch. I understand how in the first case Vout is zero, but in the second case(the switch is open), the textbook states that RL is a pullup resistor when it seems to me that the resistor actually decreases the voltage between Vout and ground. The textbook further states that RL provides a logical 1 output when the MOSFET is off but I can't understand how since Vout is not parallel to RL. Am I missing something?

CMOS inverter circuit

CMOS inverter circuit

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  • \$\begingroup\$ Just to clarify, this is not CMOS, it's simple NMOS (with a passive pullup). CMOS would have a second, actively-switched transistor in place of the pullup. \$\endgroup\$ – Dave Tweed Nov 8 '13 at 4:25
  • \$\begingroup\$ @DaveTweed Sorry, I should have said MOSFET instead of CMOS everywhere in my question. The textbook doesn't mention CMOS for this circuit. Does this have any implications on the answers below? \$\endgroup\$ – hondaman Nov 8 '13 at 5:22
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You're missing the resistance connected to vOUT. Yes, this resistance will create a voltage divider with RL, resulting in a voltage smaller than VS.

However, if the resistance is very high, such as that of a CMOS input, the resultant voltage will be close to 5V.

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  • \$\begingroup\$ So is the textbook wrong when it says that the resistance $R_L$ provides the logical 1 when the MOSFET is off? \$\endgroup\$ – hondaman Nov 8 '13 at 3:06
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    \$\begingroup\$ @hondaman: No, it's correct. In a CMOS circuit, all "logical 1" means is a voltage greater than 0.7 times the supply voltage. This will be true if the output resistance is at least 2.34 times as large as RL. \$\endgroup\$ – Ignacio Vazquez-Abrams Nov 8 '13 at 3:09
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In the second case ask yourself what level will the output come to if you removed the transistor from the circuit. the answer is: that the \$R_L\$ will pull the output to the upper rail. In this case the output resistance of the circuit is simply \$R_L\$ and for the most part in CMOS logic the loads are capacitive (i.e. the gates of subsequent transistors) so you will see a RC charge curve.

In the first case I think you've understood that the transistor is basically shorting the output to ground.

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  • \$\begingroup\$ The key to understanding this is to figure out how much current flows through R_L -- and the corresponding voltage drop across it -- in each case. A resistor has negligible voltage drop if only negligible current is flowing through it. \$\endgroup\$ – Dave Tweed Nov 8 '13 at 4:27
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I believe I was confused because the author failed to mention two components from the circuit examples: The input impedance at the input pin Vout, and the fact that the MOSFET element acts as a resistor in the OFF state.

MOSFET OFF state

In the first case(diagram above), the pull-up resistor has a much less resistance than the input impedance and the voltage drop across it is minimal compared to the impedance connected to Vout. This allows the difference between Vs and Vout to be minimal and maintaining Vout near Vs.

MOSFET ON state

In the second case(diagram above), the pull-up resistor has much higher resistance than the resistor equivalent to the MOSFET element(closed switch) and therefore the voltage drop mainly occurs at the pull-up resistor thus minimizing Vout. That way Vout remains close to GND.

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  • \$\begingroup\$ @DaveTweed Do you think this answer makes sense? \$\endgroup\$ – hondaman Nov 8 '13 at 20:22

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