During manufacture, integrated circuits are tested at varying frequencies and temperatures to categorise them into speed grades. However, why don't all ICs come out the same and work the same? They all come from the same photolithographic mask, right? Am I missing something?
Modern ICs are REALLY small. Tolerances are huge during processes such as ion implantation and oxide growth. At such small sizes, these things can't be treated as anything but a probabilistic process. Lines also tend to be smeared due to the feature size being the minimum possible given the wavelength of light. When you get worst-case performance in a bunch of these different steps, then you get a non-functioning IC.
Companies don't design the IC so that it functions at the worst-case - it would be too costly. So instead they do Monte Carlo simulation of the manufacturing parameters, estimate a yield, and do testing after the fact.
Typical "design corners":
Source: What I remember from my IC manufacturing class.
There isn't really a "worst case" - manufacturing IC's is a statistical process, there will be some (small) percentage of transistors that are a very long way from typical speed (imagine a statistical distribution curve drawn here). The distribution of speeds for the two types of transistors in CMOS (NMOS and PMOS) don't correlate well.
Thus, they pick those 4 corners: Fast/Fast, Slow/Slow, Fast/Slow, Slow/Fast out of their two transistor speed yield curves.
The further out from typical they choose to make the corners, the higher their yield, but the more difficult it is to design. If the corners are too far apart, design for operation at the 4 corners takes too much development time and can increase the die size. Increasing the die size will decrease yield.
The four corners often form more of a parallelogram than a rectangle. If both types of transistors, across one whole die, are all very fast, the part will probably work, maybe well beyond the rated speed, and same for both transistors getting slower - the part will work, but at a very slow speed. The difficult corners are the fast/slow and slow/fast.
The design is indeed fully simulated at typical/typical, and the four corners. Monte Carlo simulation is used to check some of the intermediate combinations.
To increase yield, they can sort the die into bins after manufacture and thus sell the slow/slow parts that would otherwise be thrown away, and sell the fast/fast parts for a premium.
And yes, some manufacturers will use fuses to restrict a part to a certain speed grade. Because manufacturing yield curves and market demand being uncorrelated functions, sometimes they have to down-grade parts.
Mostly what krapht said. I'd add that parts are getting so small that even without variation in geometry, the number of doping atoms per transistor are also becoming small, so simple statitical variation means some will be faster and some lower, and the gain also varies. You'll end up with some that either can't work, or can only work at say a slower clock rate. Also you might see some computers offered with say a three-core chip. Such a chip is probably a four-core chip, but a faulty core has been disconneted in postprocessing, and the chip sold as a cheep 3banger. I would add, nothing wrong with that, if that's the capability you need, then the manufacturers bad luck is our gain.
IC chips are just shrinked to the point where they "barely" work.
You can make chips on 3um process with nearly 100% good rate and very little variation, but it's just too expensive (and slow).
For analog functionality, sometimes the chip can be intentionally hobbled and the same die sold cheaper with not-so-good performance. Blowing on-chip fuses to reduce bias currents (for example) can reduce the overall performance of the chip.
For digital chips that are required to run at speeds approaching the capabilities of the manufacturing process, final test will weed out the best performers from the not-so-good performers and 'bin' them accordingly. Differences in speeds are usually caused by statistical variations in the manufacturing process.