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I have been studying about inverters for a while. In the book that I was reading, inverters have been explained according to the type of load connected to the drain of the driving transistors ie. resistive load, e-type nMOS load and d-type NMOS load. enter image description here enter image description here In both of the above circuits, if a low input voltage is fed to the gate of the driving transistor the o/p will be high because current does not pass through the load or driving transistor and the o/p is simply Vdd.

When the input voltage is high current passes through the load and driving transistor and a low o/p is obtained because minimal voltage drop occurs in this case. In neither of the above cases does having a load seems to be of any benefit.The loads seem to be simply contributing to power dissipation during linear mode operation and area . Why then are they connected in the first place?

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  • \$\begingroup\$ I know the images haven't been positioned properly. I've tried hard but in vain. If anyone knows how to adjust them be my guest! \$\endgroup\$ – Vineet Kaushik Nov 9 '13 at 17:35
  • \$\begingroup\$ I think the load you are talking about is not the external load applied to the pin of the invertor. \$\endgroup\$ – Andy aka Nov 9 '13 at 17:41
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If the bottom "driver" transistor is turned off, the output will just be disconnected from ground - it will not be high unless something, somewhere, pulls it high, and the load resistor or upper transistor will do this.

There are "open collector" or "open drain" gates that do omit the internal load, but when you use them, you have to add an external load, or depend on something else in the circuit to pull the output up.

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  • \$\begingroup\$ I understand what you're saying but having a hard time visualizing how the voltage drop across the load takes place without connecting it to the ground.Could you please explain me your answer with an equivalent circuit diagram? \$\endgroup\$ – Vineet Kaushik Nov 9 '13 at 18:35
  • \$\begingroup\$ @VineetKaushik: When the driver transistor is conducting, current will flow through the load resistor and the driver transistor to ground - nearly the full supply voltage will be developed across the load resistor. When the driver transistor is off, no current will flow through the load resistor, so there will be no voltage developed across it, making the output high. \$\endgroup\$ – Peter Bennett Nov 9 '13 at 19:42
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As you pointed out, this makes a poor inverter. It wastes power when the NMOS is on and edge slew rates are asymmetrical. When the NMOS turns off the output is pulled high with that diode connected device (which truns off near the rail) and iwhen the NMOS turns on it slams the output to ground. That's why the circuit that is actually used is shown in this list of CMOS circuits.

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The MOSFET the input signal is connected to is a transconductance element, a voltage to current converter. When the voltage at it gate passes beyond a certain threshold, it starts to draw current from its drain terminal, but this effect does not automaticly set the voltage at its drain terminal. In order to convert this current to a voltage you need a load element, most simply a resistor, or a diode connected MOSFET (enahncement mode or depletion mode) or a MOSFET working in the linear region of operation. All three cases will have different voltage transfer characteristics and the down side of all three cases is that they consume some kind of "static" power, in the on state.

Then, comes the beauty of the CMOS inverter. It has 5 regions of operation and only in the middle three transition regions it consumes any kind of power. Not consuming any static power whatsoever is what makes the CMOS inverter (or the CMOS gate) the modern staple of integrated circuits.

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