How is it possible that in a LPC3141 MCU the MCU has frequency 270MHz while the 12MHz quartz crystal is used in oscilator (inside the clock generation unit)? Makes no sense to me...
Could anyone please explain.
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3 Answers
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This is very common for processors for a variety of reasons. First, the clock tends to be the highest frequency signal in a system, so using a lower frequency oscillator will reduce radiated RF interference. Second, generating the actual core clock frequency on-chip means that the clock speed can be configurable. Lowering the clock speed in CMOS saves power, so by giving the CPU the ability to control its own clock rate, the software can scale the CPU speed as needed to reduce power consumption. This is also done on your desktop or laptop computer - the core runs at 2 to 3 GHz, but nothing on the motherboard runs anywhere near that fast except for serial busses (SATA, PCIe, and USB 3).
This clock generation is done with a device called a PLL (Phase Locked Loop). Most PLLs contain a voltage controlled oscillator (VCO), one to three dividers, a phase comparator, and a filter. The basic idea is to lock the output of the VCO onto an integer multiple of the reference clock frequency. The main part of the PLL generates the drive voltage for the VCO. This is done by dividing down the output of the VCO and performing a phase comparison with the reference clock. If the phase is leading or lagging, a positive or negative error voltage is produced. This voltage is then integrated in the loop filter and then passed to the input of the VCO. If the phase is leading, the VCO control voltage will be lowered and the VCO frequency will decrease. If the phase is lagging, the VCO control voltage will be raised and the VCO frequency will increase. Eventually, the divided VCO output and the reference clock will match in phase and frequency, and the PLL will be locked.
This method can only generate integer multiples of the clock frequency. If the reference oscillator is 12 MHz, then a division by 2 in the PLL will result in a multiplication by 2 to get a 24 MHz output frequency. A division by 3 will produce 36 MHz. Division by 4 will produce 48 MHz, etc.
Adding another divider at the input or output allows for fractional clock rate generation. Division by 2 and the multiplication by 3 in the PLL would produce 18 MHz. Division by 2 and multiplication by 5 would produce 30 MHz. Division by 2 and multiplication by 45 would produce 270 MHz.
Another consideration is that the frequency range of the VCO is often limited. This can prevent generation of frequencies that require large dividers because then the VCO frequency would be too low or too high. Adding another divider so that both the reference input and PLL output can be divided mitigates this problem somewhat so the PLL can generate a wider range of frequencies. So long as the division is not a prime number, it can be split up between the input and output dividers so the VCO is working in its operating frequency range.
answered Nov 10, 2013 at 18:16
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3\$\begingroup\$ The PLL is not restricted to integer multiples, because you can put a divider on the reference as well. Or you can use a pulse-swallowing counter. \$\endgroup\$ Nov 10, 2013 at 18:33
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1\$\begingroup\$ Yeah, I mentioned that. With only one divider, you only get integer multiples. But if you add more dividers, then you can generate fractional clock rates. With three dividers, you can make sure you're working within the range of the VCO over a wider output frequency range. A pulse-swallowing counter is not a good idea for a clock, though, as it will greatly increase jitter. \$\endgroup\$ Nov 10, 2013 at 19:18
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This is done with a so-called phase locked loop multiplier, see also wiki. A small voltage controlled oscillator (VCO) in the microcontroller is run, which has specially been designed to run stably around the desired operating core frequency. This frequency is then divided down through a cascade of flip-flops and compared to the crystal frequency. The resulting error is fed back to the VCO to correct it. When both frequencies are eventually in phase, they are said to be phase-locked and the MCU clocks can be driven from the VCO.
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Inside an IMU there are hardware multipliers that multiply the input clock of 12MHz to higher values. This can be achieved with something called a Phase Lock Loop. Imagine something like this chip the NB3N502 (datasheet) inside the micro controller.
Lean more about PLL and clock multiplication on wiki:
