I have designed a FPGA based DDS that creates digital signals between 0-70MHz. Now I want to convert my digital data into analog. As the base frequency is 200MHz, I need a high performance parallel DAC with minimum 200MSPS. As I widely searched, such DACs are plentiful but I couldn't find one without a latch. All I found work like this: data is sent to D0-Dx -> a clock latches the data -> conversion is done.

If I want to have a DAC with this system, my output frequency will be reduced to 1/2 ( one clock for D0-Dx + one clock for the data latch).

Anyone knows a part with such properties ( something that works like DAC80xx , but in high frequencies, something like this:) ?

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  • 4
    \$\begingroup\$ Why do you need to divide by 2 to use a registered DAC? There's no reason you wouldn't be able to do it at full speed, and using a DAC that has a register will give you a much cleaner output. \$\endgroup\$ – Dave Tweed Nov 11 '13 at 0:10
  • \$\begingroup\$ If you cannot get your FPGA to output a suitable 200MHz latching signal then you probably made an error when choosing your FPGA... \$\endgroup\$ – Laszlo Valko Nov 11 '13 at 0:28
  • \$\begingroup\$ If you really want a product recommendation, it would help to say the bit depth you want. \$\endgroup\$ – The Photon Nov 11 '13 at 5:23

If you're using a Xilinx FPGA, use an ODDR output buffer to generate an output clock signal at the same rate as the internal clock. Other FPGAs should have similar features.

ODDR oddr_dac_clk (
    .Q                (dac_clk),
    .C                (clk),
    .CE               (1'b1),
    .D1               (1'b0),
    .D2               (1'b1),
    .R                (1'b0),
    .S                (1'b0)

Or you could just forget the DAC, and build an R-2R network yourself. Definitely would be a lot cheaper.

  • \$\begingroup\$ I have tried R2R. It is perfect in lower signals but awful in MHz range. I think using ODDR + negedge of triggering signal is a good idea. I will try! \$\endgroup\$ – Aug Nov 11 '13 at 5:34

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