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I'm not looking for a hardware language description of the flip flop, but the logic gate level to implement.

In verilog, the equivalent I'm looking for is

always@(posedge clk or negedge reset)
begin
    if(~reset)
      Q <= 1'b0;
    else if(~load)
      Q <= D;
    end

I've looked at: http://reviseomatic.org/help/e-flip-flop/4013%20D-Type%20Flip%20Flop.php and http://www.csee.umbc.edu/~squire/images/dff.jpg

the problem with the above implementation is that after I set a value to Q (D=0,Q=0,load=0) with load(set in picture) = 0, then when i set load high load = 1 on the next clk cycle, i get (D=x,Q=1,load=1). In order words, changing load from true to false will change the value of Q, but I want Q to hold it's previous value.

What is a flip flop that would hold it's value on Q after it has been set and enable is set high?

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You've been looking at incorrect components: D type flip-flop is used to sample the D input on each clock cycle, but you want to use load signal in order to enable sampling. Please note that the signal set which you wanted to use as load has different funtionality - it causes the output to go high (regardless of the value of D).

What you are looking for is D Flip-Flop with Enable. There are two simple approaches to add this functionality to a regular D-FF.

Feedback:

Adding a MUX which is controlled by Enable signal. On each clock edge the flop will either sample the new value, or the old value (which is equivalent to keeping an old value).

enter image description here

Clock gating:

Instead of MUXing the input to the flip-flop, you may simply disable the clock when you do not want to sample a new value. This approach is widely employed in order to reduce the power consumption (no clock -> no activity -> no active power consumed).

As pointed out by @Supercat in the comments, clock gating is the more sophisticated technique which requires a bit more expertise because it presents additional delays in clock path.

enter image description here

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  • \$\begingroup\$ A flop with an enable is different in some very important ways from a flop whose clock is externally gated. Among other things, the setup/hold/min-propagation/max-propagation times on a flop with an enable are cleanly specified from the rising edge of the clock; if the clock is gated outside the flop, a 5ns uncertainty in the gate's propagation time could turn a flop whose values would be e.g. 4/1/2/6 (which if run at e.g. 40Mhz (25ns period) could accomodate logic propagation times from the previous latch of 0-15ns) into one whose values would be 4/6/2/11 (requiring logic propagation times... \$\endgroup\$ – supercat Nov 11 '13 at 16:44
  • \$\begingroup\$ ...to be in the range of 4ns-10ns. Of critical importance is that when using the flop with enable, there is no minimum time requirement for the logic between flops, but when externally gating the clock there is. Another issue to consider is that an enable signal will generally only have to meet the setup/hold times relative to an active clock edge, while a separately-gated clock will have to avoid having a falling edge of the enable signal near (before or after!) an active clock edge. Clock gating is safer in devices that are 2-phase clocked, but I've not seen 2-phase clocks used much lately. \$\endgroup\$ – supercat Nov 11 '13 at 16:49
  • \$\begingroup\$ @supercat, indeed, clock gating presents additional factors which should be taken into account, but these factors are known and there are solid techniques for handling them. For example, one of the optimizations available in Synopsys Design Compiler is to automatically convert enables of FFs into clock gating. \$\endgroup\$ – Vasiliy Nov 11 '13 at 17:50
  • \$\begingroup\$ My impression was that in many FPGA devices, most logic has no specified minimum propagation time except that if two flops are controlled by the same designated clock bus, the propagation time one one flop's output, plus any logic through which it flows, will meet the other flop's hold-time requirement. If flops are not through a designated clock bus, propagation times may vary arbitrarily. Worse, unless one forces physical implementation of a circuit node (using a flop flop will force this), it's possible for logic fed by the node to have a negative propagation delay relative to it. \$\endgroup\$ – supercat Nov 11 '13 at 17:58
  • \$\begingroup\$ Certainly some devices include circuitry within their clock buses to allow them to be gated safely, but I'm unaware of any that allow the output of a flop whose clock generated using "random logic" to be safely latched by any other flop controlled by the same master clock edge. Do some devices allow that? \$\endgroup\$ – supercat Nov 11 '13 at 18:00

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