# Arithmetic shifting in verilog

I am going through the book Verilog HDL by Samir Palnitkar.

I see that there are two types of shifting, the normal and the arithmetic.

But I was not able to understand the difference between them.

It was given that for a=0, b=-10, the output for c= a + (b>>>3) is -2. How is this possible. What is the output if we use normal shifting.

Bitwise shifting happens in a finite space, although negative values actually require an infinite space to fully accurately represent.

If we shift in a 0, not only the value but also the sign can change:

0b0110 (6)  -> 0b0011 (3)
0b1110 (-2) -> 0b0111 (7)


This is known as a logical shift, since it strictly follows the logical definition of "shifting", that is, moving the existing bits one position towards the LSb.

If we shift in the same value as the MSb, we change the value but retain the sign:

0b0110 (6)  -> 0b0011 (3)
0b1110 (-2) -> 0b1111 (-1)


This is known as an arithmetic shift, since the value is (approximately) divided by 2 regardless of the initial sign.