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I'm restoring a Model H Skee-Ball machine, and these old models have a bunch of hardcoded settings and unreliable switch detection, so I want to replace the main control circuitry with something Arduino-based, but keep the other circuitry, like the seven-segment display circuitry.

So I've been analyzing the schematics, but I'm confused about the display circuitry. The schematic for the display is below, and here is the full set of schematics for the whole machine: http://arcarc.xmission.com/PDF_Misc/SkeeBall%20Model%20H%2002.pdf

Skee-Ball Model H Display Schematics

I've never worked with shift registers before, but the impression I get is that for a display application, there needs to be a latch. This blog post was very helpful to me: http://www.sqlskills.com/blogs/paulselec/post/arduino-cascading-shift-registers-to-drive-7-segment-displays.aspx

The display circuitry uses 74C164 shift registers. I'd post a link to the datasheet, but I'm not allowed more than two links since I'm new. Anyway, the 74C164 doesn't have an internal latch, and I don't see any latch circuitry in the schematic. The ULN2003A is just a transistor array to power the lights of the display as far as I can tell.

Can someone help me understand how this circuit works?

EDIT: follow up, let me show where my main point of confusion is. In the datasheet for the 74C164, it shows an example waveform. Here's the example: 74C164 Waveform Example

It seems like the chip just passes through the data signal, but time delayed on each output. Because it doesn't latch, I don't see how it can work for the Model H display circuit. Every segment should get the same signal, just time delayed.

EDIT2: Is it possible that the chip sending the data only sends a clock signal while it's sending data? Would stopping the clock effectively latch the outputs?

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    \$\begingroup\$ If the shift registers are only reloaded when the display changes, there is no need for an additional latch - the 74C164s will hold the data. Depending on how fast the data is shifted throught the 74C164s, there may be some flicker visible on the display as the new data is shifted in. \$\endgroup\$ – Peter Bennett Nov 14 '13 at 20:21
  • \$\begingroup\$ The example waveform in the datasheet for the 74C164 implies it doesn't hold the data. I edited my question to provide those details. Here's the 74C164 datasheet: pdf1.alldatasheet.com/datasheet-pdf/view/53709/FAIRCHILD/… \$\endgroup\$ – Tim Sloane Nov 14 '13 at 21:19
  • \$\begingroup\$ A serial-to-parallel shift register wouldn't be much use if it didn't store the data shifted in! The waveform on the datasheet does imply that it stores, and outputs, the data shifted in, although it doesn't explicitly show a period between the last clock and the clear. \$\endgroup\$ – Peter Bennett Nov 14 '13 at 22:37
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It can work without a latch providing the unstable period while the data is shifted to all the drivers is small - you probably wouldn't notice the very quick flickering of the displays. Maybe if you could tell us the clock frequency this would help but, if it's running at 1MHz and there are 4 severn-seg displays then that's 28\$\mu s\$ for the update - not a long time at all and maybe the clock is even faster.

Item C on your first drawing holds the answer yet I don't recognize it - probably a GAL device.

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  • \$\begingroup\$ I believe Item C does hold the answer. I know it is a chip programmed by the board manufacturer, Deltronics, but I need to get my hands on an oscilloscope to poke around and confirm what the waveforms are doing. \$\endgroup\$ – Tim Sloane Nov 15 '13 at 16:21
  • \$\begingroup\$ It's solvable with logic I guess. Good luck Tim. PS the clock won't be constantly running - it will run 28 cycles then stop until ready to update. \$\endgroup\$ – Andy aka Nov 15 '13 at 16:22
  • \$\begingroup\$ Well, 32 cycles I think because the shift registers are 8-bit. Thanks! \$\endgroup\$ – Tim Sloane Nov 15 '13 at 17:56
  • \$\begingroup\$ @TimSloane - it only needs to run 28 cycles and the last four bits are don't-care-who care bits!! However, it's interesting where subsequent shift registers take their input from - I'm not sure if pin 13 is the final stage or some clever half-way point that does something subtle? \$\endgroup\$ – Andy aka Nov 15 '13 at 18:59
  • \$\begingroup\$ Pin 13 is the oldest bit, which is why I think it's 32 cycles. 8 bits need to be loaded per chip so all the bits are properly propagated down the daisy-chain. Every 8th bit is ignored, but is needed for the daisy chain. I think if they had used the first bit, pin 3, and daisy chained on pin 12, then they could have used the 28 bit method you suggest. \$\endgroup\$ – Tim Sloane Nov 16 '13 at 2:41
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If the display were using LEDs, having segments appear as they are shifted through would probably result in visible ghosting unless updates were infrequent and only happened when there was something else "distracting" going on. Such ghosting could be eliminated either by using latched shift registers or by blanking the supply to the displays while shifting was going on (having a segment that is lit before and after an update blank briefly during it will be far less distracting than having a segment which is unlit before and unlit after, but is briefly lit during the update).

It looks, however, as though your unit is using incandescent bulbs. Those are so much slower to respond than LEDs that unless you go out of your way to shift data very slowly, or need to update the display very frequently, display artifacts from the shifting aren't going to be a problem. If I were designing the circuit, even using bulbs, I would have been inclined to use latching shifters or a blanking control so as to allow digits to be rapidly switched on and off as a crude form of brightness control, but the game as designed probably never had any need to update the display more than once every few seconds.

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