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Ok this is a basic question but i am not able to figure out how does this work
1: This is the representation of the RS Flip-Flop with the truth table given in my
book
I am not able to connect the truth table to the representation as inn my knowledge every time the answer should be same, which i know that i am wrong so please help me.
2: what does Disallowed and no change stands for.
Thanks
Akash
Try starting to think from the second line.
If you put 0 to S port, it would go to 0 in the output regardless of the other input because it is an AND port. But its output is inverted since it is and NAND port, so when you put 0 in S signal, its output will necessarily goes to 1 regardless of the other NAND input.
Therefore, one of the lower NAND port inputs will be 1. Since we are in the second line of the truth table, R should be 1. So the lower NAND port will have both inputs in one (H). So its output will necessarily be zero. Then you have Q = 1 and Q! = 0.
If you make the same reasoning for the third line, you get correct results since it is the symmetrical situation.
As for the first line, you cant have correct results. Note that if we put 0 to S, we have Q = 1 (as the second line of the table). Altough if you put zero to R too, you will also have Q! = 1. This situation is called disallowed because Q should complement Q!. They always have to be different signals.
And for the last line, imagine we are in the second line again so we have Q = 1 and Q! = 0. If we put S to 1 (it was zero before), note that Q! is already zero, so changing S signal will not change the first NAND port result. So whenever you are in states 2 or 3 (second or third line), placing 1 to any of the inputs that are low, will not change the state.
A simple circuit for flip flop can be implemented by two transistors like this:
This Flip-Flop can be changed by pushing one of the buttons.
But how it works? Think there is no push button. and we just have two transistors and four resistors. When the circuit turns on, One of the transistors gos to On mode and then Saturation mode (rapidly) and when it goes to saturation mode, as its Collector feeds the other transistor's base, makes the other transistor going to Off mode. The next picture can demonstrate the feedback of Q1 collector to Q2 base and vise-verse:
Then just think that If I push the saturated transistor's base to ground, It become Off. Then as its collector goes High and turns the other transistor to saturated mode.
Note that When the transistor is Off, pushing it's base to ground doesn't make any effect to the circuit mode.
Now think that I push both of Transistor's bases to ground ; This makes both transistors go to off mode. And when I pull the keys simultaneously. One of the transistors go to saturated and other one goes to off (depending on circuit structure).
Further information:
Each transistor witch has better situation to consume power and current goes to saturation at first time. (And also when the both pushed buttons pulled up simultaneously(
If one input is high and the other is low, then the NAND gate attached to the "low" input will see at least one "low" signal and thus output high. The other NAND gate will see two "high" inputs and will thus output low. If the input that had been low goes high, its NAND gate will still have a "low" input [from the other NAND], and its output will thus remain high. The other NAND gate will continue to see two "high" inputs, and its output will remain low.
It might be helpful to draw out a truth table whose input side includes the outputs of the NAND gates as well as the two main circuit inputs.
S R Q !Q -> Q !Q
L H x x -> H L
H L x x -> L H
H H H L -> H L
H H L H -> L H
L L x x -> H H
H H L L -> H H *
H H H H -> L L *
In some of the lines of the table, the states for Q and !Q are marked with x rather than H or L. That means that if the other inputs have the indicated values, the behavior of the circuit will be unaffected by the ones marked with x's. Note also that I have marked two lines of the table with asterisks. All the other lines of the table either direct Q and !Q to output something which is independent of what they're currently outputting, or else output the same things as they're currently outputting. Either situation represents a stable state, and there can thus be no uncertainty about what the circuit should, or will, do in such cases. The two lines marked with asterisks, however, are different. They indicate that if both outputs are high, they should both be low, and if they're both low they should both be high. These represent unstable states, and it's unclear what exactly the circuit will do. If one of the inputs changes before the other, the circuit might then behave as though the inputs were HHHL or HHLH, and assume a stable state. Alternatively, since an output which switches from high to low or vice versa will briefly pass through an intermediate state (let's call it Middle), would be possible that a NAND gate where one input is High and the other is Middle might output Middle, in which case one could end up with both outputs sitting in an awkward Middle state.
In practice, most NAND gates, given a "Middle" input, will tend to output high or low, but their output will switch much more slowly than if their inputs were at valid logic levels. The net effect is that if at some time the circuit is in an HHLL or HHHH condition, it will eventually settle into either an HHHL or HHLH condition, but the time required for that to happen could exceed by orders of magnitude the circuit's normal switching time.
The reason the state with SR both low is marked as "forbidden" is that if at some point in time the circuit is in one of the well-defined states, the only way it can go into one of the "murky" states will be if S and R are both low either simultaneously, or so close together as to appear simultaneous. If one doesn't allow that to happen, one won't have to worry about what the circuit will do in its murky states.
