Assume we have a simple Verilog module with 1 input (in1) and one output (out). Please look at the truth table at the end of this question.
I want to send a signal with the voltage between 0-VCC0=3.3v to input in1=PIN3 of a FPGA ( this case XC3S400). All Vref pins of the relative bank are connected to 1.8V. Now I want to see a logic 1 on out=PIN4 when the voltage of in1 is higher than verf and a logic 0 when it is less.
I know it is a feature of single ended I/O standards that is supported in FPGAs but I don't know how to assign this vref comparison in ISE. I just can guess to write some attributes in the verilog or assigning vref in ISE (PlanAhead).
In ISE Plan Ahead , one can assign fixed vref standards ( GTL, GTLP,...). but these are fixed Vref standards. I am looking for a way to set vref to any voltage which is desired. For example can I set vref to GTL=0.8v but connect 1.8v to vref pins of the bank?