There are many timing strategies that can improve FPGA speed ( as Timing constraints , planning the clock regions ,....). One of these strategies is selecting optimal places for I/O pins and floorplanning the logics. In fact we first select best I/O places and then we can place the logics,.... This process starts from I/O placement and that's what I don't know which strategy leads to best performance.
These are strategies I thought about as a Starting Point of pin placement:

1- In the picture below ( Xilinx Spartan 3), one may select all in/outs in one bank (arrow-1) and a Global Clock for example on bank-4. This leads to minimum distance for all pins and also minimum noise from GCLK pin external leads but it is far from the GCLK line.

2- path-2: crosses GCLK path but inputs and outputs are far from each other ( I saw somewhere that horizontal pathway between inputs and outputs is the fastest way but can't recall where I read it !! )

3- path-3: being close to clock pin may impose some noise from its EXTERNAL leads and components.

There may be many other strategies that I don't know. Can anyone give me a hint or method of thinking as a start point?

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  • \$\begingroup\$ I believe you may have to try each approach and report back what you find. \$\endgroup\$
    – user16324
    Nov 17, 2013 at 10:56
  • \$\begingroup\$ @BrianDrummond I thought about that but my design includes 70% of XC3S400 gates and each try may take 1-2 months ! That's why I need somewhere to start ! \$\endgroup\$
    – Aug
    Nov 17, 2013 at 11:09
  • \$\begingroup\$ Do you have a full licence ISE or using the web pack? \$\endgroup\$
    – FarhadA
    Nov 17, 2013 at 14:35
  • \$\begingroup\$ @FarhadA Webpack \$\endgroup\$
    – Aug
    Nov 17, 2013 at 15:16

1 Answer 1


The global clock doesn't have a 'path' per se. You can go in any of the global clock pins on the chip and then route the signal from there onto one of the global clock nets. These nets are dedicated so it doesn't matter how any of the other signal nets are routed as it won't affect the global clock nets. Also, the connection to the global clock net from the pin does not involve the general routing fabric of the FPGA so long as the pin is capable of directly driving a global clock net.

I would not be too worried about the influence of the clock input on traces that aren't immediately next to the pin. If you're very worried about the clock input, then use a lower frequency oscillator on the board and get the frequency you need by using one of the DCMs in the FPGA to synthesize the higher frequency clock.

In terms of IO pin locations, what I usually do is figure out what they're going to be connected to outside of the FPGA. The software can route signals wherever they need to go inside the FPGA. And if you follow some of the design rules of thumb, all of your inputs and outputs should pass throgh IOB flip flops. This greatly helps the place and route stage by synchronizing the inputs and outputs and hiding much of the skew that occurs in the routing. The expense is a clock cycle of delay on the input and a clock cycle of delay on the output, a reasonable price to pay for synchronization.

Bottom line: most pins can go wherever it is convenient with no performance degredation. The toolchain will take care of the details. Use this to your advantage to simplify the board layout and trace routing outside of the FPGA.


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