There are many timing strategies that can improve FPGA speed ( as Timing constraints , planning the clock regions ,....).
One of these strategies is selecting optimal places for I/O pins and floorplanning the logics. In fact we first select best I/O places and then we can place the logics,.... This process starts from I/O placement and that's what I don't know which strategy leads to best performance.
These are strategies I thought about as a Starting Point of pin placement:
1- In the picture below ( Xilinx Spartan 3), one may select all in/outs in one bank (arrow-1) and a Global Clock for example on bank-4. This leads to minimum distance for all pins and also minimum noise from GCLK pin external leads but it is far from the GCLK line.
2- path-2: crosses GCLK path but inputs and outputs are far from each other ( I saw somewhere that horizontal pathway between inputs and outputs is the fastest way but can't recall where I read it !! )
3- path-3: being close to clock pin may impose some noise from its EXTERNAL leads and components.
There may be many other strategies that I don't know. Can anyone give me a hint or method of thinking as a start point?