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When designing a digital one-minute counting circuit I came across a difficult problem.

Basically, I designed the circuit to drive the (normally HIGH) clock of the 10s slot low if the 1s slot's current state was 9 (actually, just if the first and last bits are HIGH -> 1001)

The devices I am using are positive edge, so when the 1s slot returns to zero the condition is no longer satisfied - therefore the clock returns to a HIGH state and increments the 10s slot.

The problem is that I was getting double clock problems(7->8 transition and the designed clock mechanism).

It turns out that there was just enough delay in the switching between 7 -> 8 (0111 -> 1000) that the first/last bit HIGH condition is satisfied:

i.e., some combination occurs in the transition period to register a logical HIGH at the output

1001 1011 1101 1111

The temporary solution to the problem I came up with was to actually keep the clock for the 10s slot LOW until the condition where the 1s slot equals 0 (0000) is satisfied(So, essentially clock WHEN we get to the state as opposed to before). However, this solution requires too many gates (a 4-input NOR minimum). My previous design was actually fed from another part in the design that is already present, so it didn't require any additional circuitry.

Any ideas on a more efficient solution?

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The IC's used in this design are the 74LS47 (7Segment decoder) and the 74LS163 (4-bit binary counter). The pull-down resistor inclusion is a mechanism to set the counters to 00 and hold while the switch is closed.

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The '163 is a synchronous counter (with synchronous reset), so there's absolutely no excuse for trying to use it with a "ripple"-style clock.

Instead, you should have the clock inputs of both counters connected to your clock source, and you should use the "Enable P" and "Enable T" inputs to control when the second counter advances.

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If you're having problems with switching speed on a slow switching circuit, the simplest solution is to slow it down. I would suggest using your original idea, but add a series RC lowpass filter (series R, then shunt C to GND) right before the clock input pin with a time constant (R times C) on the order of a milisecond or so. This should filter out any very short runt pulses that are being generated. If that doesn't work, crank up the time constant to 10 ms or even 100 ms. Too high and there will be a noticable delay, though.

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  • \$\begingroup\$ The clock is not the problem. The problem lies in the switching speed of the gates. The clock goes HIGH, for example, and there is a brief moment of time as the bits are switching from 0111 -> 1000 that the first and last bit are on at the same time. \$\endgroup\$ – sherrellbc Nov 18 '13 at 7:00
  • \$\begingroup\$ I'm referring to the clock input pin on the counter that's skipping a step due to the glitch. The RC circuit will 'eat' the glitch pulse to prevent the counter from incrementing when it's not supposed to. \$\endgroup\$ – alex.forencich Nov 18 '13 at 9:47
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The way I see it, you're causing problems for yourself by using multiple clock domains, and worse, deriving a clock from data. The problem with data is that it has to settle. That's why we have separate clocks. A combinatorial circuit which evaluates some variables and then drives a clock invites trouble.

Secondly, if you're going to kludge it, at least do it right. You cannot detect a 9 by noting that the first and last of four bits bit are 1. If you want a signal which fires when there is a 9, you must evaluate all four bits earnestly and trigger that signal only when they are 1001.

There is no reason not to design this in such a way that a single clock is distributed to all the chips. Then it's a matter of running the clock slowly enough that all inputs and outputs settle before each edge arrives.

Read the data sheet. The TI one clearly says "The carry look-ahead circuitry provides for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count enable inputs P and T must be high to count [...]".

It sounds like these chips are intended to be hooked up together easily. You can prevent the upper digit from counting up on the next clock edge by de-asserting its count enable inputs. Whenever the lower digit is nine, your circuitry can enable the upper digit chip to count, and also set up the lower digit to perform a synchronous reset.

When the next clock edge arrives (to all chips), the upper digit counts up, and the other flips to zero.

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  • \$\begingroup\$ This is true. However, I think if you're working with discrete logic for something as simple as this, adding all of the extra logic required to get it all in one clock domain is not always the best solution. Yes, it may not be able to perform at 10 MHz, but in this case it seems like the circuit only needs to run at 0.1 Hz so an alternative method should perform just as well while requiring fewer chips. \$\endgroup\$ – alex.forencich Nov 18 '13 at 9:57

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