I am creating a custom CPU and would like it to be programmable on the fly instead of hard coded in VHDL. The issue I am having is that without initial code for the CPU to run, ISE will trim large amounts of my logic away. I have tried using the 'S' attribute to declare my signals and variables as 'not trimmable', but that does not work on all of the signals. I have also tried setting the keep hierarchy option in XST, but even that fails sometimes (complains that there is a conflict with the KEEP settings and will trim anyway). Is there a way for me to tell ISE to not trim anything at all without having to create a default program that runs through every opcode?

Here is one of the errors I am seeing:

WARNING:Xst:638 - in unit cpu_instructor_copy Conflict on KEEP property on signal brain.current_opcode<0> and brain.stack_pointer<14> brain.stack_pointer<14> signal will be lost.

Without the S attribute, the stack_pointer will just get removed.

I have the following at the top of my 'brain' process

variable stack_pointer : integer range 0 to (2**mem_addr'length) - 1 := stack_origin;
attribute S : string;
attribute S of stack_pointer : variable is "YES";

Thank you in advance!

Edit: Here is the actual code (no attributes in it currently as those are on my personal test copy)

Edit 2: The problem was fixable by changing my program from a constant to a signal, adding a new process that could 'program' the CPU with serial (at least that's what the design thinks), and setting the Map process to not trim unconnected signals. I will post the code a little later. Thank you all!!

  • 3
    \$\begingroup\$ You need to make sure the logic you want to keep is actually used. Expose some interface to the instruction memory to the outside, and it won't get cut out. \$\endgroup\$
    – darron
    Nov 21, 2013 at 3:51
  • \$\begingroup\$ Either to the outside, or initialise the instruction memory with test code (write a suitable init function for the purpose) \$\endgroup\$
    – user16324
    Nov 21, 2013 at 10:20
  • \$\begingroup\$ @BrianDrummond I was afraid that was going to be the only acceptable answer. Is init code like that normal for CPUs in an FPGA? \$\endgroup\$
    – Proto
    Nov 21, 2013 at 13:39
  • \$\begingroup\$ @darron Thanks for the info. It rather sucks that I can't just disable trimming. Any idea why trimming can't just be disabled? \$\endgroup\$
    – Proto
    Nov 21, 2013 at 13:40
  • 3
    \$\begingroup\$ Proto: Because a very basic function of the synthesis tool is to simplify the logic. There are inputs, some process, and output. If there's something in the process that cannot affect the output, then it's completely pointless and SHOULD be removed. It's like telling someone to write a three page paper, let nobody know or witness it, then erase all but the first sentence. You need to give meaning to the logic being simplified away by having it actually affect the result. This is usually not hard to do. You could add a function that returns the checksum of all memory, for instance. \$\endgroup\$
    – darron
    Nov 21, 2013 at 19:39

1 Answer 1


You can prevent trimming with an option on the Map process properties. In ISE, expand the 'Implement Design' section, and right click 'Map' and select 'Process Properties'

Uncheck the option for 'Trim Unconnected Signals' (-u). Click the help button for more information on all the options displayed here.

From the help:

Trim Unconnected Signals

Specifies whether or not to trim unconnected components and nets from the design before mapping occurs. Leaving this option blank is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, set this property to False (checkbox is blank) to map unconnected components and nets.

By default, this property is set to True (checkbox is checked), and unconnected components and nets are trimmed.


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