How does a system bus work?

I don't understand how can a circuit avoid input/output issues with a bus. I included an image to better explain my thinking.

enter image description here

The circuit has 2 general purpose registers connected to a system bus. The left wires of each GP register is input and the right wires is output. Currently, the input is going inside the output, causing logisim to mark the wire red (error). What are the solutions to avoid this?

Here is the black-box for the registers.

enter image description here


Instead of AND gates you need to use tristate drivers. These drivers go to a high-impedance state when they are not enabled, which allows some other device on the bus to control the bus signal voltages. Presumably, the control logic allows only one register output to be enabled at any given time.

Logisim calls these drivers a "controlled buffer", by the way.

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  • \$\begingroup\$ Interesting! I have never played with those... In fact, I don't even know what a tristate is! I'll check that out. \$\endgroup\$ – Justin D. Nov 21 '13 at 23:06
  • \$\begingroup\$ I learned these as tri-state buffers. They also have a truth-table associated with them: For an input A and B where A is the signal and B controls the buffer portion. When B is low (for active-high buffers), the buffer "outputs" high-Z, so no signal can feed into it. When B is high, the output is A. (Just an example) \$\endgroup\$ – Shabab Nov 21 '13 at 23:11
  • \$\begingroup\$ They are called "tristate" because they drive three distinct conditions on the wire rather than "binary" which relates to two distinct conditions. The conditions are logical 1, 0, and HiZ. Logic 1 and 0 are the usual signals. HiZ is an open circuit, the pin is electrically isolated (at a high impedance, aka Z) from both power rails, or effectively disconnected from the wire. \$\endgroup\$ – RBerteig Nov 21 '13 at 23:53

Joe Hass covers the traditional way, replacing the AND gates with tristate logic. This is the way things were done with TTL chips in the 1970s and it is still quite common at the PCB level.

However inside an FPGA, tri-state buffers are no longer supported (except at the external pins) since about the start of this century. (ASICs differ in this respect; thanks to Joe Hass for the correction) The synthesis tool may accept a circuit description based on tri-states, but implement it by transforming the circuit into something entirely different ... usually the first stage is a row of AND gates connected to the Enable as in your example.

If your register genuinely has AND gates on the enable line, then it is a more recent design, and you need an extra stage of logic to create the bus.

That stage is simply an OR gate on each bus bit with N inputs, one input for each source (GP register etc) driving the bus. The outputs from each source are simply ORed together, and the OR gate output drives the bus. The N-input OR gate can be implemented in several ways - e.g. as a tree of 2-input OR gates if that's what your logic system offers.

This works because if one Enable is high, all other sources are driving 0 on the bus.

It is more reliable than the tri-state approach because if several Enables are high, the result is meaningless nonsense (several outputs ORed together) instead of a short circuit across the power supply (where one source is '0' and the other is '1'), possibly causing a small fire...

Both approaches work : but if you are designing logic inside an FPGA or ASIC, this one is strongly preferred.

(An alternative way of eliminating tri-states is based on an N:1 multiplexer. If you draw out the usual implementation of a 2:1 multiplexer you will find the two approaches are essentially the same).

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  • \$\begingroup\$ Brian, with all due respect, multiplexing with tristate drivers is still done in ASICs although you have to be very careful with the leakage currents at deep submicron. Using multiplexers is more common in FPGAs because the fabric favors Boolean logic implementations. The suggestion that bus contention could cause a fire is just silly...I hope you were kidding. And I can assure you that my practical experience includes custom CMOS ICs in this century. \$\endgroup\$ – Joe Hass Nov 22 '13 at 13:17
  • \$\begingroup\$ Thanks for the correction re: modern ASIC flows. Edited to fix. And I was largely joking about the "small fire" though I suspect you will concede that with 74S or perhaps a large enough failure on something newer, burnt fingers or device failure are possible. \$\endgroup\$ – Brian Drummond Nov 22 '13 at 13:22
  • \$\begingroup\$ @JoeHass: One thing I've wondered about when doing low-power designs with transistor-level CMOS is whether it would be helpful to internally use two clocks which switch at slightly different times, and have a bus "float" very briefly around each clock edge, so as to ensure that anything which wants to drive a line high will be completely switched off before anything that wants to drive it low starts to switch on. I understand that dynamic logic isn't liked much these days, but such an approach would seem little different from most dynamic logic, in that... \$\endgroup\$ – supercat Nov 22 '13 at 19:39
  • \$\begingroup\$ ...most dynamic logic expects a node's capacitance to hold a state between system clock edges, whereas the goal here would be to use the capacitive float to hold a state for an internally-generated time which would probably be closer to a nanosecond. \$\endgroup\$ – supercat Nov 22 '13 at 19:40

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