# Verilog syntax question

Something like this:

a=b?c:d ; would make a=c, if b=1, else a would be made equal to d;

But what would doing the same thing on an array do? Like this:

assign a = (|b[10:8])?8'hff : b[7:0]; // to limit the max value to 255 Does it check each of the 3 bits, 8, 9 & 10?

• That will take the bit wise or of b[10], b[9], and b[8]. If any of those are 1 then you'll get 255 in a. Otherwise you'll get b[7:0]. Is that what you want?
– Doov
Nov 22 '13 at 3:11

## 1 Answer

a = ( | b[10:8] ) ? 8'hff : b[7:0];

When | is used as a prefix, it is a reduction operator. That means it operates on all the bits of the vector that follows it. So what's happening here is the bits of the vector b[10:8] are being or'ed together to get a single bit result.

That result is used to choose whether to assign the constant 8'hFF, or the lower 8 bits of b to a.