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I'd like to formally understand this simple biasing circuit:

circuit diagram

Let V+ be the supply voltage, Vi be the input voltage at the seemingly unconnected terminal of the capacitor, and let Vo be the output voltage at the junction between the resistors and capacitor. Let S be the impedance unit (i*omega)

using VI relations and Kirchoffs laws: (V+ - Vo) / R1 - Vo/R2 + (Vi-Vo) * C*S = 0

which after rearranging gives:

Vo = (V+/R1 + ViCS) / (1/R1 + 1/R2 + C*S)

decomposing the numerator it becomes clear that the biasing term is:

= (V+/R1) / (1/R1 + 1/R2 + C*S) = V+ / (1+R1/R2 + R1CS)

Does the amount of bias really depend on the driving frequency? At DC, S=0 and everything reduces to a voltage divider regardless of the voltage at Vi.

(Sorry for the eye-sore math. Is it possible to do math input on this website like it is on math.stackexchange ?)

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  • \$\begingroup\$ Addtionally, I'd appreciate it if someone would embed the schematic in the question. I do not yet have sufficient rep. \$\endgroup\$
    – Gus
    Jan 18, 2011 at 4:29
  • \$\begingroup\$ It is not yet possible to use TeX, but we're working on it. \$\endgroup\$
    – tyblu
    Jan 18, 2011 at 4:45
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    \$\begingroup\$ it's j * omega... i is for mathematicians not engineers :) \$\endgroup\$
    – vicatcu
    Jan 18, 2011 at 15:13

1 Answer 1

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quick explanation: The biased voltage can be regarded as a superposition of the contribution from V+ (calculated above, called biasing term) and the contribution from Vi (the other term, with VisC in the numerator):
Vo = Vo,V+ + Vo,Vi = V+/[R1(1/R1 + 1/R2 + sC)] + (VisC)/(1/R1 + 1/R2 + sC), where

  • Vo,V+ = V+/[R1(1/R1 + 1/R2 + sC)] and
  • Vo,Vi = (VisC)/(1/R1 + 1/R2 + sC)

When one uses superposition, they redraw the circuit with all other voltage sources shorted and other current sources opened (other than the one being considered). This means that when considering the contribution from V+, Vi is grounded, so the frequency[-ies] in the Vo,V+ term is that present in V+, which should be near zero for a DC source. Using the same arguments, the frequency in the Vo,Vi term is that present in Vi.

Superposition makes sense for many reasons; one of the arguments I've made to justify it to myself is to look at Fourier analysis, which shows that any signal can be decomposed into the superposition of sinusoids, and those sinusoids can be extracted by filtering out the others; the Gibbs phenomenon is often seen in practice as ringing.

To be more precise though, we should take into account the load resistance that would be connected between Vo and ground.


simplified analysis: The capacitor in this circuit is called a DC blocking capacitor, because it doesn't pass any DC signals. A common and useful technique to analyzing circuits that separate high frequency AC and DC signals like this is to approximate the blocking capacitor as an open circuit to DC signals and short circuit to AC signals. This greatly simplifies analysis of more complicated systems. For mid-band frequencies -- those for which the capacitor presents an impedance comparable, over 5%-10%, to that of R1||R2 -- the complicated impedance formula needs to be used. For low frequency signals, where the capacitor impedance is more than ~100·R1||R2, the cap can be regarded as an open circuit. Of course, this depends on the sensitivities of your circuitry, but that will be apparent if these considerations are of value.

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  • \$\begingroup\$ gives an excellent answer. The key point here is that the resistors determine the DC bias (as a plain old voltage divider) that gets added to the AC signal at V_in. The size of the capacitor should be such that it has a negligible impedance in the frequency range of interest (so it's generally a very small valued capacitor) \$\endgroup\$
    – vicatcu
    Jan 18, 2011 at 15:32
  • \$\begingroup\$ Thank you tyblu for mentioning superposition! Superposition makes sense because the voltage-current relation of all of the elements in the network are linear. (In the case of the capacitor, exciting the voltage as a sinusoid, the current is a sinusoid with the same frequency) I am not sure I understand the small correction. I agree that the impedance of the capacitor is 1/sC, but in node current sum (Kirchoff's law) equation, I am adding all of the currents, so I'm dividing the voltage across the device by the impedance of the device. \$\endgroup\$
    – Gus
    Jan 18, 2011 at 17:23
  • \$\begingroup\$ @Gus, You're quite right! Thanks for not taking what people say at face value! \$\endgroup\$
    – tyblu
    Jan 18, 2011 at 19:38
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    \$\begingroup\$ @vicatcu, I think you mean a large value cap, and were thrown off by my juvenile math mistake :) \$\endgroup\$
    – tyblu
    Jan 22, 2011 at 0:02
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    \$\begingroup\$ ah yes right larger the capacitance, lower the impedence... \$\endgroup\$
    – vicatcu
    Jan 22, 2011 at 2:55

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