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I was having a doubt related to tristate buffers. I know that a tristate buffer allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit.

But does don't understand which transition time High impedance to conducting or vice-versa when connected on a bus should be larger for the tristate buffer

It will be helpful if you provide me with a circuit of tristate buffer with transistors or gates

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A tristate buffer has a certain minimum time from when the enable is asserted to when its output impedance starts to fall (the drivers start to turn on). Also, it has a certain maximum time from when the enable is negated to when the drivers are fully off (high output impedance).

If the former is not greater than the latter, then you cannot use the same (well, inverted) enable signals directly for two buffers on the same bus; you need to guarantee the timing by other means — either by using different clock edges, or perhaps by using a delay line.

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  • \$\begingroup\$ Even if the output isn't "fully" off, one may as a practical matter be able to get away with using the device provided that the specified maximum current that one device would try to output while high would not exceed the maximum allowable pin current for either device, and provided that the excess current drawn in such a situation didn't pose a problem. Not typically a good idea, but if the bus state changes seldom and a device has e.g. 4mA current-limited outputs, it might not be too bad. \$\endgroup\$ – supercat Nov 26 '13 at 22:11

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