To build a latch and its interface with alarm, you need an extra AND gate and OR gate.
The latch consists of an AND gate followed by an OR gate with both of its inputs labeled as R̅ and S respectively. We follow the convention that a variable with a "bar" on top is active low and a variable with no "bar" on top is active high. Hence R̅ is active low, S is active high.
The interface is complete when we connect output I from alarm to inputs labeled "2" on both AND gate and OR gate.
How does the combined alarm/interface circuit work?
When the alarm is triggered, I is set (I = 1). This signal drives OR gate input 2 or S to 1. The OR gate is active high. S = 1 sets the OR gate, so Q = 1. Then Q = 1 drives input 1 of AND gate via feedback, which together with I = 1 set the AND gate, so P = 1. The alarm will continue to be on until it is cleared by the master reset A = 0. Upon reset, I is cleared (I = 0). The AND gate is an active low circuit. I = 0 resets the AND gate so P = 0. The same signal I = 0 drives the second input of the OR gate which together with P = 0 clears the OR gate so Q = 0. This completes the alarm operation cycle.
Rationale for Interface Design
The AND OR configuration is known as R̅-S latch with 2 independent inputs R̅ and S. Let's define A2 (R̅) be the second input of AND gate, and O2 be second input of OR gate. In general A2 is labeled as reset input since A2 (R̅) = 0 resets AND gate, and O2 (S) is labeled as set input since O2 (S) = 1 sets OR gate. To avoid unexpected operation, it is important to specify how alarm interfaces with the latch. In this case, we choose to tie the A2 and O2 inputs together, so that A2 = O2. If this condition is violated, the combined circuit will not function properly. For example, if A2= 0 and O2=1, the alarm will be set when it is supposed to be reset (false alarm). Similarly, if A2 = 1, O2 = 0 and P = Q = 0, the alarm will be reset when it is supposed to be set (false disalarm).
Even though R̅S type of latch is known to have an unpredictable behaviour, this design does not suffer from such uncertainty as our interface design excludes that possibility.