# Latched Logic Circuit

I'm having trouble with part of a build I have to do. I've built this circuit: $I = A\bullet(B + C + D + E + F)$ The $+$ is OR, $\bullet$ is AND, and I'm using 2-input OR gates. The output signal is for an alarm.

I need a latched output - I need to derive a simple logic circuit using 1 OR and 1 AND logic gate, that could be added to the alarm output signal. It should latch the alarm output signal once the alarm has been triggered, and the latched condition should require a cycle of the master switch to reset the alarm.

I googled for answers but couldn't find any... e.g. A site I love for Digital Electronics and Circuit Theory is http://www.wisc-online.com

If someone could tell me what I need to do, or point me in the right direction that'd be great.

• If I needed to bake a cake and I only had anchovies and bread can I still bake the cake? You probably need to explain why you need to make the latch from "1 OR and 1 AND logic gate". – Andy aka Nov 28 '13 at 23:28
• The build is part of my digital electronics lab work in college. We're told to use 1 OR and 1 AND gate in the assignment sheet. I notice we don't have any SR/RS latches in our component kits, so maybe that's the reason I'm not sure. Either way I don't know how to build a latch.. – somers Nov 29 '13 at 8:13

You need a device called an RS or SR latch. Basically, it has a 'set' and a 'reset' input and it will hold the output state indefinitely when neither set or reset are asserted. You can connect all of your inputs through OR gates to the set input, and then a 'master reset' switch to the reset input. If any input triggers the alarm, the latch will stay put until the reset button is pressed.

• I'd like to second that an SR latch is the right kind of device for what the O.P. wants to do. However, an SR latch requires NAND or NOR gates. However, it looks that the O.P. has got only AND and OR. – Nick Alexeev Nov 28 '13 at 23:36
• Thanks a lot for your reply alex. I'll look into what you've said but as I'm new to electronics I'm curious - will an OR gate and AND gate do the same thing as an RS/SR latch? – somers Nov 28 '13 at 23:37
• I think you can make an RS latch with an AND gate and an OR gate, actually. It's not usually done as far as I know. It will just be a bit asymmetrical as one of the inputs will be active high and the other one will be active low. It also will not give you complementary outputs. You need to have some feedback, though, otherwise the circuit can't hold any state. Take one AND gate and one OR gate, connect them in a loop (output of one to one of the inputs on the other) then either output will be the latch output, the other AND gate input is inverted reset, and the other OR gate input is set. – alex.forencich Nov 29 '13 at 0:56
• Thanks very much alex, I'll try that. In the circuit I've built the final output from the AND gate goes to an LED, to indicate that the alarm has been triggered. Should the latch be placed between the LED and the output from the AND gate? i.e the output from the AND gate goes into the latch, and the latch output goes to the LED. Hope that makes sense. – somers Nov 29 '13 at 8:25
• @alex.forencich: The AND/OR latch is not all that uncommon; it's sometimes useful in cases where e.g. one has signals that indicate "input over 1/3 rail" and an "input over 2/3 rail". An And/OR latch may be used to implement hysteresis in fairly straightforward fashion. – supercat Dec 4 '13 at 20:57

To build a latch and its interface with alarm, you need an extra AND gate and OR gate.

Latch Design

The latch consists of an AND gate followed by an OR gate with both of its inputs labeled as R̅ and S respectively. We follow the convention that a variable with a "bar" on top is active low and a variable with no "bar" on top is active high. Hence R̅ is active low, S is active high.

Interface Design

The interface is complete when we connect output I from alarm to inputs labeled "2" on both AND gate and OR gate.

How does the combined alarm/interface circuit work?

When the alarm is triggered, I is set (I = 1). This signal drives OR gate input 2 or S to 1. The OR gate is active high. S = 1 sets the OR gate, so Q = 1. Then Q = 1 drives input 1 of AND gate via feedback, which together with I = 1 set the AND gate, so P = 1. The alarm will continue to be on until it is cleared by the master reset A = 0. Upon reset, I is cleared (I = 0). The AND gate is an active low circuit. I = 0 resets the AND gate so P = 0. The same signal I = 0 drives the second input of the OR gate which together with P = 0 clears the OR gate so Q = 0. This completes the alarm operation cycle.

Rationale for Interface Design

The AND OR configuration is known as R̅-S latch with 2 independent inputs R̅ and S. Let's define A2 (R̅) be the second input of AND gate, and O2 be second input of OR gate. In general A2 is labeled as reset input since A2 (R̅) = 0 resets AND gate, and O2 (S) is labeled as set input since O2 (S) = 1 sets OR gate. To avoid unexpected operation, it is important to specify how alarm interfaces with the latch. In this case, we choose to tie the A2 and O2 inputs together, so that A2 = O2. If this condition is violated, the combined circuit will not function properly. For example, if A2= 0 and O2=1, the alarm will be set when it is supposed to be reset (false alarm). Similarly, if A2 = 1, O2 = 0 and P = Q = 0, the alarm will be reset when it is supposed to be set (false disalarm).

Even though R̅S type of latch is known to have an unpredictable behaviour, this design does not suffer from such uncertainty as our interface design excludes that possibility.