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I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs bits than there are physical pins, so Quartus II cannot compile (the fitter complains the FPGA does not have enough pins).

As I understand, in order to make Quartus II happy, I need to some input pins of my module as virtual. These are the constraints in my .sdc that I have tried:

set_input_delay -clock clk_i 0 [large_bus]
set_instance_assignment -name VIRTUAL_PIN ON -to large_bus

Even with those constraints, Quartus II is still complaining. How can I make a "dummy synthesis" of my Verilog module to check for timing?

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Altera supports virtual IO and in order to get it to work, you must assigned them the property VIRTUAL_IO on (as you have done), but if these pins are connected to any signals in your design, it will no longer work.

Check out this web site that describes the steps needed to get this to work:

Declaring Virtual Pins in Quartus

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  • \$\begingroup\$ When you say "connected to any signals in your design", do you mean "connected to any input or output signals of your top level module"? \$\endgroup\$ – Randomblue Dec 2 '13 at 9:58
  • \$\begingroup\$ Yes, Altera Quartus (at least the one I used last year) didn't see those as virtual pins and if the signals didn't have a driver or source, it would remove them from the design even with the Virual IO setting on those signals. I was told this was fixed, but I have not tested it myself. I used VIO in many IPs with up to 900 IOs and they work very good. \$\endgroup\$ – FarhadA Dec 2 '13 at 10:57
  • \$\begingroup\$ Thanks. When I do that, I get "Ignored Virtual Pin assignment" warnings. \$\endgroup\$ – Randomblue Dec 2 '13 at 10:59
  • \$\begingroup\$ Check out this answer on Altera: altera.com/support/kdb/solutions/rd03092009_568.html you might have such IOs in your design. \$\endgroup\$ – FarhadA Dec 2 '13 at 11:17
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Altera has a nice example on their website with a script that will make all pins virtual. I use this a lot in complex system with lots of modules for sub-system timing estimation.

  load_package flow

  proc make_all_pins_virtual {} {

     execute_module -tool map

     set name_ids [get_names -filter * -node_type pin]

     foreach_in_collection name_id $name_ids {
        set pin_name [get_name_info -info full_path $name_id]
        post_message "Making VIRTUAL_PIN assignment to $pin_name"
        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
     }
     export_assignments
  }

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/tcl/all_virtual_pins.html

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The way I've done this in the past is make a wrapper with a single in pin and a single out pin, along with clock and reset pins.

Then wire a big shift register up to the in pin, and wire the real inputs of your module to the bits of that shift register. Do similar with your outputs and an out shift register.

That way you only need 4 pins - the functionality of your design will not be correct, but you can get timing information.

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  • 2
    \$\begingroup\$ While this will work, I think the whole of virtual pins is to avoid this hack. \$\endgroup\$ – Randomblue Nov 29 '13 at 15:17
  • \$\begingroup\$ Yes, I'm sure you're right. Unfortunately, I've never had much joy :( \$\endgroup\$ – Martin Thompson Nov 29 '13 at 15:18
  • \$\begingroup\$ Altera was first with virtual I/O for FPGA and Xilinx followed by a similar approach in their 14.3 version of Vivado. \$\endgroup\$ – FarhadA Dec 8 '13 at 15:18
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In Vivado, when you want to perform module analysis, i.e. implementing a module in a bottom-up approach for resource estimation, for instance, you can run synthesis with the following option:

synth_design -mode out_of_context -flatten_hierarchy rebuilt -top <top_module_name> -part <part>

The option -mode out_of_context ensures I/O placing is disabled. It enables, for instance, the synthesis of modules with a pin count higher than the device pin availability. In Quartus, setting the virtual pin option is the equivalent way? Or there is a more appropriated way?

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I had the problem, that I needed to rerun map in quartus to accept the assignments before I could run the fitter. So one map to get the node names, setting the pin assignments, another map to accept the assignments and then running the fitter:

load_package flow
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
    set pin_name [get_name_info -info full_path $name_id]
    post_message "Making VIRTUAL_PIN assignment to $pin_name"
    set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
execute_module -tool map
execute_module -tool fit 
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