I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs bits than there are physical pins, so Quartus II cannot compile (the fitter complains the FPGA does not have enough pins).
As I understand, in order to make Quartus II happy, I need to some input pins of my module as virtual. These are the constraints in my
.sdc that I have tried:
set_input_delay -clock clk_i 0 [large_bus] set_instance_assignment -name VIRTUAL_PIN ON -to large_bus
Even with those constraints, Quartus II is still complaining. How can I make a "dummy synthesis" of my Verilog module to check for timing?