# CMOS inverter : Calculation of Vd

simulate this circuit – Schematic created using CircuitLab

Consider the CMOS circuit shown, where the gate voltage Vg of the N-MOSFET is increased from zero while the gate voltage of P-MOSFET is kept at 3V. Assume that for both the transistors the magnitude of threshold voltage is 1V and the product of transconductance parameter and the (W/L) ratio is 1mA V-2.

Now my question is, for a small increase in Vg beyond 1V, what will be the region of opertion for both the MOSFET's? How do we calculate the drain voltage?

This is a homework problem, right?

First of all check whether transistor conduct.

• PMOS conducts when $V_{SG}>|V_T|$.
• NMOS conducts when $V_{GS}>V_T$.

If any of them is in cut-off, then the solution is very simple, right? If both are not in cut-off then we proceed.

You got two separate transistors. This means that you can write two separate current equations. This complicates by the fact that MOSFETs have different equations for "linear" and "saturation" modes of operation. There are four possible combinations for modes of PMOS-NMOS: linear-linear, linear-saturation, saturation-linear, saturation-saturation. You'll need to guess here and check if your guess works - if it doesn't, then you'll get unsolvable equations. In this case you simply check the other combinations. However, just by inspection of the circuit you may be able to eliminate some of the possibilities.

What the unknowns are in these equations? Hint: there are up to four of them (currents, voltages).

You can't solve for four unknowns having just two equations. Too bad. But if you can relate some of the unknowns to each other, you may be able to reduce their number. Try to see what constraints are imposed by the schematic (current relations, voltage relations, ...).

The combination of modes which provides you with a solution for $V_d$ is the answer (together with the solution itself).