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I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals.

I know how to constrain clocks, for example:

create_clock -name clk_i -period "157 MHz" [get_ports clk_i]

I also know how to constrain input signals relative to a clock, for example:

set_input_delay -clock clk_i 0 [get_ports data_i*]

However, I don't know how the (asynchronous) reset line should be constrained. How are reset lines constrained?

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I usually synchronise my async reset through a delay line of a few flipflops (relying on the FPGA configuration to have cleared them), and only use that synchronised reset (even if I'm using it as an asynchronous reset).

In Xilinx-land, the tools can trace the timing through from the clock used in the delay line to the reset input (either sync or async) of your flipflops, so no explicit timing constraint is necessary. I'll be surprised if Quartus cannot do the same.

I would not recommend attempting to distribute a truly asynchronous reset across the chip.

If you do, you have a small chance of the release of the async reset being very close to the clock edge. Due to the delay across the chip, some flipflops will see it on one clock edge, and others will just miss it and see it on the next clock edge. In the worst case, those flipflops will form part of a state register (for example) and "part" of the state machine will come out of reset before another part! Bad things tend to ensue. But only occasionally, which makes it a nightmare to figure out!

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