This is a good example of mismatch in results between simulation and synthesis.
If you will synthesize this code and run a test on FPGA - it will work (at least you'll not see constant hash value). However, in simulation it behaves differently:
always @(*) construct means "evaluate the following block of code any time any of the signals used on the right hand side of the assignment change". In your code these signals are:
- If none of the above signals change (which is the case you're describing, right?) - the block will not be evaluated by simulator and the assignments won't be made.
Once again - synthesis tool will produce the correct logic for this code, therefore these kind of bugs are very dangerous.
There correct way to handle this is to define a clock signal and use a sequential
always @(posedge clk) construct.
Furthermore, it seems that you have at least two combinatorial loops in your code. Even if they are intended - this is very bad practice. You want to avoid using any synthesizable comb loop.
However, by inspection of your code, it seems that circular reference here is just for convenience - maybe it will not synthesize into comb loop. In this case you have two options:
- Find an equivalent form which does not use circular reference
- Use Verilog
The first approach is the correct one - Verilog is not a programming language, and the statements you are using to describe logic must be maximally similar to the inferred logic. However, this approach may be tricky, since many algorithms are written in software forms. Therefore you might use the second approach, in which case the code will look like this (not tested):
always @(posedge clk)
hashValue[15:0] <= calcNewHashValue(hashValue[15:0], poly[15:0], data_in[3:0]);
calcNewHashValue is the function encapsulating the
for loop from your code.
Once again: if synthesis tool warns you about comb loops you mustn't use this design. In this case either think of other algorithmic implementation, or spread the calculation on several clock cycles.
You may also want to read this paper in order to get a deeper understanding of Verilog simulators behavior.
Except for that, your coding style is very bug-prone. As a guideline, I suggest you will define a separate
always block for each signal. In other words - just one signal is assigned over in
always block. Make exceptions only where you can't handle it other way, and think carefully before each such decision.