Why do you assume that with high speed links, a high pin count is not required ? Maybe for your application.
From the several projects I worked on and other I just have been in touch with, here is the scope of use of a FPGA/CPLD with high-speed links :
Used as an I/O expander with a CPU/SoC/DSP. The FPGA will, for example, connect multiple high speed links like Gigabit ethernet and will be connected to the CPU through a higher speed link like PCI Express or custom LVDS bus. The FPGA is used as a smart multiplexer.
In this case, a high pin count is needed but with few logic gates and internal memory.
Used alone : the FPGA serve as the CPU, it will make all the processing. In this case a high pin count and many logic gates and high internal memory or external memory for the processing (which need pins...)
For example I worked on an aerospace deterministic ethernet switch with a high end FPGA : 28 ports @ 1 Gbps + 2 PCI Express links and 2 QDR memories for routing tables and statistics. A very high pin count and a lot of logic gates was needed.
If you don't fit in this two use case, maybe you have a very specific application that the FPGA vendor are not interested in.
Nevertheless I understand your point of view, I worked personnally on a project where we needed a FPGA with many transceivers (up to 20, with up to 10Gbps...) but few logic gates (as it will be used as a smart multiplexer) and we haven't found a reference with a small footprint, many transceivers and few GPIO pins.
As you don't give information on your application (link speed ?) you can take a look at Lattice ICE40 family. I think this will fit your needs.
Edit (explanation about high pin count) :
FPGA tend to have packages with high pin count for some of these reasons:
Most of the FPGA have a JTAG access with dedicated pins. Depending of the model these pins can be used as GPIO (if the JTAG is not used) or are totally dedicated. You will also have some pins used for reset, programming, etc. Sometimes you can have around 10 pins for configuration purpose, if you are lucky these pins are muxed so you can use them as GPIO and configuration pins.
This is the most pin-consuming use. FPGA I/Os tend to be organized by banks regrouping pins. As FPGA are used for prototyping, I/O voltage is bank-dependant : each bank has its own power pins so you can have 3.3V signals on some GPIO and another bank with 2.5V or 1.8V. This is very useful when your FPGA make an interface with a recent processor (1.8V or 2.5V I/O voltage) and you have 3.3V chips on your board, the FPGA can be used as a voltage shifter.
Also when you have transceivers on your FPGA, the pins are shield with GND pins around.
When you take a FPGA with a BGA package you will have around 30% of the pins used for Power and GND. TQFP and SMD package tend to have less power/GND pins but are more limited in terms of signal integrity.
Also if you have a small package with few pins, let's say 16 pins. If you count about 4 pins for configuration, 4 pins for GND, and 2 pins for core power and I/O power, you already use 10 pins, or 8 if you use only 2 pins for GND, so you will only have 8 dedicated I/Os pins.