1
\$\begingroup\$

I recently completed a PCI-E Gen 1.0 line card design. The line card consisted of 4 Spartan 6 FPGAs sharing one PCIE reference clock. Early on in the design there was a decision to solely use the PCIE reference clock to clock all the internal logic from this PCIE reference clock and hence no on board crystal was used. The FPGAs interface to a bunch of servos on the other side over 10/100MBS interface and the FPGAs used the DCM to divide the PCIE- Reference clock to 25MHz and used for the MII and the PHY interface. There was a lot of Receive Data valid errors on the PHY interface which was attributed to the PCIE reference clock and its inherent jitter of 30KHz to 33KHz(Spread spectrum modulation). We decided to turn off the SSC function in the host software and we stopped seeing the receive error and things are back to normal. I wanted to ask and see if others had different experience using the PCIE-ref clock for clocking all FPGA logic including the 25MHz PHY interface. I was under the impression that the FPGA's DCM would clean up the PCI- reference clock after it gets in to the PCIE MGT hard macro before it was divided down. This is my first FPGA design and hence would appreciate some insight.

\$\endgroup\$
  • 1
    \$\begingroup\$ What was the datasheet spec for the required input clock? What Phy are you using? In my last design, I chose to put an oscillator on the board specifically for the Ethernet phy because the FPGA DCM/PLL would not meet the clock jitter spec. \$\endgroup\$ – stanri Dec 4 '13 at 9:32
  • 1
    \$\begingroup\$ @stacey,The PHY is DP83849 and the jitter spec for the TX reference clock is 1.4nS. The FPGA Max input clock period jitter 1nS max. I think the DCM in the FPGA can account for high frequency deterministic jitter of up to 1nS. But i dont see any documented evidence of it keeping track of a clock that is wandering around 30-33KHz increments on purpose. Like I mentioned things are better now that we have turned the spread spectrum functionality off and the clock is fixed at 100MHz +/-300PPM. \$\endgroup\$ – ultrasounder Dec 4 '13 at 18:52
2
\$\begingroup\$

All a DCM can do is add jitter - it's a tapped delay line, so the output clock can jitter as the taps change. And for the same reason it can't remove any jitter that is already there.

If you want to "clean up" the clock signal, you need to use a PLL - check the datasheet to see if the FPGA PLLs can cope with the spread-spectrum PCIe clock. Or use a dedicated clock cleaning PLL device.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.