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I am now reviewing a paper about hardware implementation and it says by cropping the 128*96-pixels from 160*120-pixels, the size of the frame memory (SRAM) can be reduced to 1/10.

I don't get it.

Does anybody know how this works?

(EDITTED)

The image is first downsized to half... So. 320*240 -> 160*120 -> 128*96

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If you store an image in an SRAM, generally you want to be able to split the address bus into an x and a y component. To do this, at least one of them must be a power of 2. For 320 x 240, you have to round 320 up to 512 to get a power of 2. 512 x 240 is 122880. If you shrink it down to 128x96, it's more efficient because 128 is already a power of 2 so you can fit it in a 128 x 96 = 12288 byte SRAM. There's your factor of 10.

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  • \$\begingroup\$ Splitting addresses into X and Y components is common, but not universal. Something like 320x240 narrowly exceeds a power of two total number of pixels, but if it were instead something like 320x192, one could e.g. have the top 4 bits of address be (x8 or y7):(x8 or y6):(x7 xor y7):(x6 xor y6). That would yield a different address for every valid combination of x6-x8 and y7-y8. \$\endgroup\$ – supercat Dec 5 '13 at 20:14
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128*96 = 12288 pixels

160*120 = 19200 pixels

thus there is no 1/10 relationship but 1.56..

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  • \$\begingroup\$ Is the size of the SRAM proportional to the size of the image(MxN)? \$\endgroup\$ – IKS Dec 5 '13 at 14:29
  • \$\begingroup\$ @IKS: Yes, unless you reduce the bits-per-pixel (fewer bits to indicate colour) or introduce compression (rare for in-memory storage) \$\endgroup\$ – RedGrittyBrick Dec 5 '13 at 14:34
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The minimum amount of RAM required to hold each row of an image will generally the number of pixels per row times the number of bits per pixel [most systems use the same number of bits for every pixel, though some historically have not]. In some cases, especially when this amount is close to being a multiple of some particular power of two, it may be rounded up [e.g. a display that's 640 pixels wide with 24 bits per pixel would require 15,360 bits per row, but for ease of addressing some such displays would round that up to 16,384 per row].

Some display subsystems require that the number of bits per pixel and the number of bits per row must both be powers of two. A display that was 160 pixels wide with 24 bits per pixel would thus end up requiring 8192 (256x32) bits per row even though less than half those bits were used. Scaling things back to 128 pixels of eight bits each would shrink the memory requirement to 1024 bits--an eightfold reduction in the amount of memory required [though less than a four-fold reduction in memory utilized].

Incidentally, when the number of bytes per row is something over a power of two, and the number of rows is a multiple of three, it's sometimes helpful to push the number of bytes per row by an "extra" power of two but subdivide the display vertically into thirds. This approach is used on the Apple II series of computers, which have 40 bytes per row. The top third of the display uses bytes 0-39 of rows that start 128 bytes apart; the middle third of the display uses the same rows as the top third, but uses bytes 40-79 of each; the bottom third uses bytes 80-119 of each row. The hardware for doing this is simpler than would be the hardware to deal with a non-power-of-two number of bytes per row, though software which has to draw across the boundaries between sections is a little more complicated.

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