A common approach is to use a chain of 74HC595 or similar serial-in-parallel-out shift-register chips, and drive the chain using the clock-output and MOSI wires of an SPI port as well as one "ordinary" I/O pin. The SPI clock-output pin should connect to the shift-clock input of every shift register, and the ordinary I/O pin should connect to the register-clock input of every shifter. One shifter should have its data-in connected to MOSI; a second shifter should have its data-in connected to the data-out from the first. If there's a third shifter, its data-in should be connected to the data-out from the second, etc.
Using this approach, three processor pins can connect to any number of shift-register chips which collectively control any number of pins. To set the outputs, send to the SPI port the data which are supposed to go in all the shifters, sending the data for the shifter that's furthest away from the processor first. Once all the data have been sent, pulsing the register-clock pin high and then low will cause all of the shift register outputs to change simultaneously. One may change as many or as few outputs as desired on each step; the only factor limiting the number of outputs one may control is the need to respecify the state of every output any time one wishes to change any of them.
If you only need certain groups of outputs to be able to change simultaneously, it may be helpful to have multiple independent shift-register chains. All of the chains can share the clock-output and MOSI pins (using one register-clock output per chain) if one ensures that once code starts shifting data to a chain, all the data for that chain will be sent and strobed before the SPI bus is used for anything else. If one has 240 outputs which need to change occasionally and 16 that need to change somewhat more often, giving the chips controlling 16 frequently-changing outputs their own register-clock pin will mean that changing those pins will only require sending two bytes out the SPI rather than 32.
