4
\$\begingroup\$

I'm working on a design, and this will be my first attempt at a buck-boost regulator.

I need the output to be variable because my application calls for different voltages under certain conditions.

The buck-boost regulator I'm considering is the LT8705

enter image description here

Most of the reference designs I've seen have used either a fixed output, or in some cases, I've seen where a potentiometer was added but never a digital one.

I haven't yet decided on specific digital pot, but let's assume I decide to use this MCP4021/2/3/4 to replace the 392k and 10k resistors connected to the FBOUT pin on the right side of the image shown above. I haven't calculated what exact resistors I'll need so for the purpose of this question, assume that the digital pot's resistance is in range.

enter image description here

Max current through the resistors is 2.5mA. My max output voltage would be 28V. If I set my pot to be greater than 11.2kohm, the current would be < 2.5mA through it.

$$ R_{min}= \frac {28V_{max}}{2.5mA_{max}} = 11.2k\Omega$$

If this is true, then my next question is what considerations should I be aware from the following snippet from the datasheet

enter image description here

..set by an external feedback resistive divider carefully placed across the output capacitor.

What would 'carefully placed' entail ? Would placing this IC near the regulator potential disrupt its behaviour ? Any additional feedback would be appreciated.

Thanks!

\$\endgroup\$
  • \$\begingroup\$ if you haven't looked at that already, look at the PCB layout recommendation on pp. 35-36 in the LT8705 datasheet. \$\endgroup\$ – Nick Alexeev Dec 8 '13 at 6:01
  • \$\begingroup\$ @NickAlexeev yup I did. Looked a design app note from them too. Couldnt find the answer to my question about digital pots / digital pot layout with this regulator. \$\endgroup\$ – efox29 Dec 8 '13 at 6:29
  • 2
    \$\begingroup\$ The datasheet for that (and most, I think) digital pot requires that the voltage on the pot terminals be between Vss and Vdd, with a maximum Vdd of 5.5 volts - if your desired output voltage is above 5.5 volts, you can't use this digital pot. \$\endgroup\$ – Peter Bennett Dec 8 '13 at 8:03
  • 1
    \$\begingroup\$ I'd be very wary of this. It's the sort of thing that may work perfectly well most (or all) of the time but if it gave problems I'd not be surprised. It's usual to place a small capacitor across the upper feedback resistor (from Vout to FB pin). Deep-ending on other factors this may cause immense improvements to transient response. If the digital pot has characteristics which vary dynamically with Vout transients (perhaps due to noise getting into switch control ccts or whatever) then it may have the effect of a semi randomly variable AC coupling across the upper FB R. Murphy says this is ... \$\endgroup\$ – Russell McMahon Dec 8 '13 at 11:33
  • 1
    \$\begingroup\$ ... more likely to produce bad results than good ones. | General layout of components in the loop response governing sections of switching regulators is often important. The aim is to get signals to where they should go and avoid signals coming from unintended places and to not load or modify signals in unintended way. Digital pots offer more ways of getting this wrong than do most 2 terminal passive resistors. -> So - try it, watch it carefuilly, don't let it fool you. -> Report back. \$\endgroup\$ – Russell McMahon Dec 8 '13 at 11:36
3
\$\begingroup\$

Be aware of the capacitance to ground on each pin of the digital pot. The spec you embedded in your question suggest a range in the order of about 100pF. I don't know the exact switching frequency of your proposed application but, if it were 200kHz, 100pF would have an impedance of about 8 kohms (reactive) and this might be significant compared to the feedback resistor values you intend to enact with the digital pot. This could mean that you get a highly unstable circuit (worst case scenario) or, a lot of ripple voltage (more probable scenario) or absolutely no problem at all.

There isn't enough information in the LT data sheet to call this one so I'd advise setting it up with standard resistor values to cover the range you expect and testing it by adding 100pF caps across those resistors just to see if they introduce oddball behaviour. Other than that it should work just fine.

If it does got belly-up on you there is another alternative and that is to "offset" the feedback voltage with a current sink/source thus "conning" the LT8705 into thinking it needs to raise (or lower) it's mark-space ratio. The current sink/source can be controlled via the pot you want to use and because the pot would be "isolated" from the actual feedback node the capacitance problem wouldn't be an issue. Current sink/sources can be designed with very low capacitances (sub 5pF) so this should be OK. Remember, the standard feedback resistors won't introduce more than 1 or 2 pF and a bit of track might add another 2 pF hence my concern.

\$\endgroup\$
2
\$\begingroup\$

You should be fine with a DPOT in the voltage divider. However, do not replace the entire divider with a DPOT. The voltage on the DPOT pins cannot exceed the power rails. I would suggest replacing only the lower half of the voltage divider with the DPOT; this will ensure that the maximum voltage the DPOT can see is the reference voltage of 1.2 volts. In terms of location, just put it reasonably close to the controller chip. If you put it farther away, then you might get some issues with parasitic capacitance and inductance.

\$\endgroup\$
  • \$\begingroup\$ Ah yes, I missed that. Good catch. Thanks for the tip. \$\endgroup\$ – efox29 Dec 8 '13 at 8:17

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.