# Design an amplifier with maximum voltage gain

Problem description is as follows: Design an amplifier with maximum voltage gain without output saturation.

The following diagram was given:

I've tried doing a T-model for the first part that goes up to C2, and I got the following:

Vo=gmVgs(RE1)

Vin=gmVgs(1/gm)

Resulting in the following gain:

Av = vo / vi = gm*RE1

I have a feeling this result doesn't seem right.

For the sake of honesty, to say that I'm not sure what direction to take or how to attack this problem would be an extremely mild way to put it.

Another issue (?) I'm having is that I'm looking on the manufacturer's datasheet for the MOSFET I'm using, and there is no value for the transconductance paramater kn*(W/L), which I need when calculating the drain current in DC analysis, and 'gm' in small-signal analysis.

If the real question is "fill in the component values to get maximum output voltage without clipping for the given input signal.", then this question can't be answered except in the specific case of making C4 zero (removing it). Can you see why? Also, you don't have any choice over the DC gain. You can make the AC gain higher than 1, but if you're stuck with this circuit topology you really can't make it all that predictable. Can you see why that is?

If I was given this problem, I'd probably write a answer explaining why this topology is unreasonable for achieving the goal, which is also too vague to be a real spec. I'd back that up with a detailed analisys and critique of the circuit, explaining exactly what the problems are, what important specifications are missing, and why a predictable result is not possible. Maybe I'd flunk the question, or maybe I'd get extra credit. However, I'm not going to engage in irresponsible engineering just to tell the instructor what most will assume he wants to hear.

I think what the instructor wants you to realize is first what gain you actually need, then how to adjust the component values to achieve that gain.

First let's look at the gain required. The input is only specified to be "10 mV". That leaves a lot unsaid. I'd probably take that as being a AC 10 mV RMS signal. When looking at amplifier clipping, it's the peaks that matter. The first thing you should think about is what peak to peak voltage is implied by "10 mV" in this case. I'd consider that to be at least a sine wave, but if it's something like a audio signal you will need some headroom past what a sine wave would peak at for the given RMS voltage. Think about this carefully. What peak to peak input voltage are you going to assume?

Next, look at what the output can do. Q2 is biased by ground, so the extent of the collector voltage will be roughly from ground to the 10 V supply. For good design, I'd probably leave a little room so that the worst case peak-peak input resulted in about 9Vpp out.

From the above two analisys, you should be able to decide the voltage gain this amplifier needs. As others have noted already, the first stage is a emitter follower, which will have a voltage gain of basically 1. It can be used to lower the impedance of the input signal, but it's not going to provide any voltage amplification. Do all the parts really need to be there? Put another way, consider that you could specify part values as 0 (short) or infinite (open). Consider what exactly RC1 is doing for you, for example.

All the voltage gain is going to come from the second stage (the circuit around Q2). C2 helps in that it decouples the DC operating points of the first and second stages. Can you see how you don't really have much choice over the DC voltage gain of this stage, and how you don't have any choice at all over the DC gain of the whole amplifier? In fact, you're not going to get more than a DC gain of about 1 from this stage. This may not be so obvious. Take a look at it carefully and tell us why.

C4 can effect the AC voltage gain, but can you make that predictable and not a function of the frequency?

Overall, this is a much more tricky problem than others seem to taking it as. I suspect that the instructor messed up or there are additional specifications you haven't given us. Or possibly the instructor wants you to find the problems in what looks like a straight forward assignment at first glance.

• I didn't even see the 10mV input spec until I read your answer. That is a constraint I didn't consider. I'll rewrite my answer accordingly. – Alfred Centauri Dec 9 '13 at 15:42
• @ThePhoton: Doh. I keep making stupid edits to this post. I seem to break one thing everytime I fix something else. Thanks for catching that. – Olin Lathrop Dec 9 '13 at 17:49

Av = vo / vi = gm*RE1

I have a feeling this result doesn't seem right.

Your error here is that in this circuit vgs and vi are not the same thing. The input voltage is applied across the combination of the transistor's gate-source branch and the source resistor RE1.

I'm looking on the manufacturer's datasheet for the MOSFET I'm using, and there is no value for the transconductance parameter...

I'm not sure which parameter you're looking for, but transconductance itself is given as a specification:

However, as you see, the value is only specified for one particular operating condition, and is only given as a typical value.

Finally, a couple of hints:

1. Recognize that the first stage is a source follower (assuming we work with MOSFETs instead of BJTs), not a common-source stage. So provided you choose reasonable values for RE1 and RC1, the voltage gain will simply be 1.

2. When you get to the 2nd stage, realize that if C4 were absent, then you would not need to know gm to get the approximate gain of the stage. However, with C4 present (assuming it's chosen to give a low impedance at the operating frequency) this goes out the window and I think you will need to have a maximum limit on gm to be able to guarantee no saturation. Since that spec (or the equivalent, max $\beta$ on BJTs) is rarely given on real-world devices, the problem itself doesn't seem to be well-designed.

3. When you talk about saturation, you're talking about a large-signal effect. Small signal models will only take you so far with predicting this behavior. To answer this problem for the real world, you'd want to build a SPICE model and do some tolerance analysis to be sure you don't have saturation with worst-case variation of all your components.