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I'm attempting to design an H-Bridge which can supply 24V at 60A. As 60A is a lot of current I decided to parallel upto 4 FETs per leg to split the current.

I am using a MIC4102 2A driver to drive the FETs and I understand the important of keeping drive loop of the FETs small. Here's a circuit showing just 2 legs. The layout is also shown for the high-side.

enter image description here enter image description here

The layout shows the path from pin DH (pin 3) to the FETs' gates to their sources and back to pin HS (pin 4).

Since the high di/dt return current will try to stay close to it's drive path I decided to just pour a polygon beneath the drive traces (and resistors) and let the current flow back to the IC. I also annotated the layout picture above to show where I think the return path will flow (white dotted line in the picture). If it follows this pattern I think the drive loop will be quite small. There is a small error in the annotation - the white dotted line should go to pin 4 of the IC and not pin 3.

Can I count on this return path pour to reduce ringing that my FETs experience? Most datasheets which show a layout only show a single high-side FET and no gate resistor. The inclusion of the gate resistor and multiple FETs made it necessary for me to have polygon.

The H-Bridge (Only Half Bridge shown in schematic. The other half is exactly the same) is intended to drive a transformer at 20kHz and boost 24V upto 350V.

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    \$\begingroup\$ I'd put the driver as close to the average position of all the FETs as possible. I'd also put the resistors as close to the gates as possible. \$\endgroup\$
    – Andy aka
    Dec 9, 2013 at 12:39
  • \$\begingroup\$ An ambitious project. Sleep calls so I'll leave more detail to others, but: Reverse biased Schottky diodes gate to source mounted as close to pkg as possible will prevent ringing. | A gate resistor limits gate capacitor charge rate and current peak and will reduce switching rate and typically will decrease switching losses. \$\endgroup\$
    – Russell McMahon
    Dec 9, 2013 at 12:39
  • \$\begingroup\$ @Andyaka Actually it's already close to the average position. I apologize for not making this clear - the layout picture omits the low side which is on the right hand side of the driver. \$\endgroup\$
    – Saad
    Dec 9, 2013 at 12:44
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    \$\begingroup\$ Also very useful are gate to source zeners with Vzener > V_drive_gate but less that Vgs_max. WHEN Miller capacitance transfers much energy into gate from eg inductive drain load the zener allows the transient to turn the FET on - which may not be ideal but would happen anyway BUT clamps the gate below Vgsmax destruction point. This works VERY well. I've had designs that last minutes without the zener and indefinitely with it. I'd include such a zener as of right in any design with inductive load and THEN see if I can design so as to not need it. Zener Vds may be useful but has other function. \$\endgroup\$
    – Russell McMahon
    Dec 10, 2013 at 0:26
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    \$\begingroup\$ May I suggest to remove thermals when connecting poligons to MOSFET pins for the sake of lower resistance? \$\endgroup\$ Jan 3, 2014 at 3:01

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"Ringing" in your circuit may not have anything to do at all with the gate drive. I have built inverters up to 1MW at 25kHz (induction heaters), using many parallel IGBT's (and smaller power units using FET).

There is inductance (call it Lx) from your 2200uf capacitors to the transistors. Even with the best design of gate drive circuitry, you can experience "ringing" in the overall circuit. Snapping off the transistor when there is 60A flowing in the Lx can cause ringing upon your "Vbat". The ringing will be observed in many test points through-out your system.

Solution to this type of ringing is to put additional capacitors (smaller, e.g. 1uf non-electolytic) across each high side, low side transistor pair. Thus reducing the L from positive rail to negative rail in each of the paralleled transistor pairs.

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