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I am designing for a motherboard with a single PCIe x16 slot which can be bifurcated into 2 logical x8 slots with jumper settings. I am designing a board to handle the physical splitting of the port.

The manufacturer of the motherboard has told me I can't just split REFCLK (100Mhz HCSL) to 2 cards, but rather need to use a clock buffer. This adds a decent amount of extra complexity to my adapter board which would otherwise have no active components on it. Is this really necessary?

I'm told the original REFCLK is generated by Intel PCH C216 chipset, and the C216 datasheet says it supports multiple PCIe slots. If I was just designing a motherboard with C216, would I need to add a fanout buffer to support multiple slots? Wouldn't the C216's clock be able to drive multiple PCIe cards directly?

Are bifurcation adapters like this one completely passive?

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You definitely need a clock buffer. The reason is that you need to guarantee that there won't be any problematic reflections on the clock signal. The REFCLK is a differential signal that must be routed with controlled impedance. If there is a change in impedance, it will generate a reflection. A change in impedance can be caused by a number of things - vias, branching traces, stubs, etc. If you put a Y in the trace, then at that point the signal coming from the clock source will see 50 ohms differential instead of 100 ohms and several things will happen. First, the split means that you lose half of the signal immediately because one half goes down each side of the split. Second, due to the impedance mismatch, a 1/3 of the signal reflects off of the split and comes back down the trace towards the source. Presuming the clock source is properly matched, the reflected signal should be almost completely absorbed in the source. The end result is that each card gets 1/3 of the clock signal it was expecting.

Now, there is another problem that has not yet been considered. What happens if only one card is populated? Now, you have a stub that ends in one of the connectors. The signal will bounce off of the stub and come back down the trace. It will hit the Y, 1/3 will bounce back down the stub (and it will come back again, ad infinitum), and 1/3 will travel towards the connected card and 1/3 will travel back towards the clock source. The connected card will now receive two copies of the clock signal that are both attenuated (one by 1/3 and one by 1/9) and one of them delayed by twice the stub length. This can cause issues with the receiver as it is possible for it to receive more clock edges than were sent. And what if you get a reflection off of the card's receiver or what if the clock driver chip on the motherboard isn't perfectly matched? Reflections galore! Not good. So put a clock buffer on there so everything is isolated. And really, it's just one chip with a bypass cap or two and maybe a couple of resistors.

And that one you linked has a clock buffer on it, by the way. There is a TSSOP package chip sitting right between the slots right where the key is located.

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    \$\begingroup\$ thanks for the detailed answer - gives me better intuition about the issues here. I had a feeling I'd need one, but just wanted to be certain. This is a prototype board that will be assembled by hand, so just hoping to keep things simple. I was looking at a 20-pin clock multiplexer which would solve the fanout problem, but the manufacturer recommended a true zero-delay-buffer which had a PLL so it would better manage cases where the input clock was spread spectrum. It's a slightly bigger component (28pin), but I suppose more robust design and the cost is just soldering a few more leads. \$\endgroup\$
    – aberson
    Dec 12, 2013 at 15:36

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